Integra DTR-4.6 Service Manual page 78

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IC BLOCK DIAGRAMS AND DESCRIPTIONS
CS494003(Audio Decoder DSP)
PIN NO.
TERMINAL NAME/DESCIPTION
97 HDATA5, GPIO5:DSPC Bidirectional Data Bus, General Purpose I/O
98 SCLK1
:Audio Output Bit Clock:Bidirectional digital-audio output bit clock for AUDATA4, to AUDATA7.
As an output, SCLK1 can provide 32 fs, 64 fs, 128 fs, 256 fs, or 512 fs frequencies and is synchronous to MCLK.
MCLK:Bidirectional master audio clock. As an output, MCLK provides a low jitter oversampling clock.
99
VDD2:2.5V supply voltage.
100
VSS2:2.5V ground.
101
AUDATA4, GPIO28:Digital Audio Output 4, General Purpose I/O.PCM digital-audio data output.
102
HDATA4, GPIO4:DSPC Bidirectional Data Bus, General Purpose I/O
103
:Audio Output Bit Clock:Bidirectional digital-audio output bit clock for AUDATA0, to AUDATA3.
SCLK0
104
HDATA3, GPIO3:DSPC Bidirectional Data Bus, General Purpose I/O
105
AUDATA3, XMT958A:Digital Audio Output 3, S/PDIF Transmitter
106
AUDATA2:PCM digital-audio data output.
107
LRCLK0:Audio Output Sample Rate Clock
108
AUDATA1:PCM digital-audio data output.
109
AUDATA0:PCM digital-audio data output.
110
CMPCLK, FSCLKN2:PCM Audio Input Bit Clock:Digital- audio bit clock input.
111
HDATA2, GPIO2:DSPC Bidirectional Data Bus, General Purpose I/O
112
VSS3:2.5V ground.
113
VDD3:2.5V supply voltage.
114
HDATA1, GPIO1:DSPC Bidirectional Data Bus, General Purpose I/O
115
HDATA0, GPIO0:DSPC Bidirectional Data Bus, General Purpose I/O
116
CMPREQ, FLRCLKN2:PCM audio input request
117
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L 13942296513
CMPDAT, FSDATAN2:Digital-audio data input that can accept either one compressed line or 2 channels of PCM data.
118
FLRCLKN1:Digital-audio frame clock input.
119
WR, DS, GPIO10:Host Write Strobe, Host Data Strobe, General Purpose I/O
120
RD, R/W, GPIO11:Host Parallel Output Enable, Host Parallel R/W, General Purpose I/O
121
PLLVSS :PLL Ground Voltage
122
FILT2: Phase-Locked Loop Filter. Connects to an external filter for the phase-locked loop.
123
FILT1: Phase-Locked Loop Filter. Connects to an external filter for the phase-locked loop.
124
PLLVDD:2.5V PLL supply voltage.
125
XTALO:
126
CLKIN, XTALI:External Clock input / Crystal Oscillator input:12MHz crystal oscillator is connected.
127
CLKSEL:DSP Clock select input
128
CS, GPIO9:Host Parallel Chip Select, General Purpose I/O
129
A0, GPIO13:Host Address Bit 0, General Purpose I/O
130
FSDATAN1:Digital-audio data input can accept from one compressed line or 2 channels of PCM data.
131
VDD4:2.5V supply voltage.
132
VSS4:2.5V ground.
133
FSCLKN1, STCCLK2:Digital audio bit clock input.
134
SCS:Host Serial SPI Chip Select:SPI mode active-low chip-select input signal.
135
SCDIN:SPI Serial Control Data Input:In SPI mode this pin serves as the data input pin.
136
VSS5:2.5V ground.
137
VDD5:2.5V supply voltage.
138
A1, GPIO12:Host Address Bit 1, General Purpose I/O
139
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SCDOUT, SCDIO:Serial Control Port Data Input and Output:In SPI mode this pin serves as the data output pin.
140
HINBSY, GPIO8:
141
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SCCLK
142
UHS2, CS_OUT, GPIO17:Mode Select Bit 2, External Serial Memory Chip Select,General Purpose I/O
143
RESET :Master Reset Input:Asynchronous active-low master reset input.
144
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Crystal oscillator output.
x ao
Input host Message Status, General Purpose I/O. This pin is indicates that serial
y
or parallel communication data written to the DSP has not been read yet.
i
:This pin serves as the serial SPI clock input.
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