Allen-Bradley MicroLogix 1000 User Manual page 264

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MicroLogix 1000 Programmable Controller User Manual
Preface
Program File 2 of SLC 5/01 Processor at Node 3
First Pass Bit
Bit 1 of the message
word. Used for fan
control.
Operation Notes, MicroLogix 1000 and SLC 5/01 programs
Message instruction parameters: N7:0 is the message word. It
is the target file address (SLC 5/01 processor) and the local
source and destination addresses (MicroLogix 1000 controller)
in the message instructions.
N7:0/0 of the message word is the interlock bit; it is written to
the 5/01 processor as a 1 (set) and read from the SLC 5/01
processor as a 0 (reset).
N7:0/1 of the message word controls cooling fan operation; it is
written to the SLC 5/01 processor as a 1 (set) if cooling is
required or as a 0 (reset) if cooling is not required. It is read
from the SLC 5/01 processor as either 1 or 0.
Word N7:0 should have a value of 1 or 3 during the message
write execution. N7:0 should have a value of 0 or 2 during the
message read execution.
Program initialization: The first pass bit S:1/15 initializes the
ladder programs on run mode entry.
13–16
S:1
0 ] [
15
1
T4:0
2 ] [
DN
N7:0
B3
3 ] [ [OSR]
0
0
B3
] [
4
1
N7:0
] [
5
1
6
N7:0
(U)
0
T4:0
(RES)
TON
TIMER ON DELAY
(EN)
Timer T4:0
Time Base 0.01
(DN)
Preset 400
Accum 0
B3
(L)
B3
( )
1
N7:0
(U)
T4:0
(RES)
O:1.0
( )
0
END
MicroLogix 1000 controller: N7:0/0 is latched; timer T4:0 is
reset; B3/0 is unlatched (rung 1), then latched (rung 3).
SLC 5/01 processor: N7:0/0 is unlatched; timer T4:0 is reset.
Message instruction operation: The message write instruction in
the MicroLogix 1000 controller is initiated every 1280 ms by
clock bit S:4/6. The done bit of the message write instruction
initiates the message read instruction.
B3/0 latches the message write instruction. B3/0 is unlatched
when the message read instruction done bit is set, provided that
the interlock bit N7:0/0 is reset.
Communication failure: In the MicroLogix 1000 controller, bit
B3/10 becomes set if interlock bit N7:0/0 remains set (1) for
more than 4 seconds. In the SLC 5/01 processor, bit B3/10
becomes set if interlock bit N7:0/0 remains set (1) for more than
4 seconds. Your application can detect this event, take
appropriate action, then unlatch bit B3/10.
Bit 0 of the message
word. This is the
interlock bit.
4-second Timer
Latch Instruction –
This alarm notifies the
10
application if the interlock
bit N7:0/0 is not set after
4 seconds.
0
O:1/0 energizes
cooling fan.