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REGISTERS
100BASE-TX CONTROL REGISTER : REGISTER 17
[TXCR] 11h
15
14
13
12
11
0
0
0
0
•
IDLESEL
•
DHybrid
•
DTMode
•
BP_SCR
•
BP_4B5B
•
BPNRZI
•
LPBK
PHY ADDRESS REGISTER : REGISTER 18
[PAR] 12h
15
•
PHYAddr
7-12
10
9
0
0
LPBK
BPNRZI
Select the number of IDLE
Bits for descrambler syn-
chronization:
Hybride Mode
Descrambler Test Mode
Bypass Scrambler
Bypass 4B5B
Bypass NRZI
Loopback
Reserved
Phy Address
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
8
7
6
5
0
0
BP_4B5B BP_SCR DTMode
00 = 22 IDLE bits (default)
01 = 32 IDLE bits
10 = 42 IDLE bits
1 = Use both IDLE and IIIJK to achieve Descrambler synchronization.
0 = Use only IDLE to achieve Descrambler synchronization.
1 = Descrambler Lock timeout value is equal to 260 bits.
0 = Descrambler Lock timeout value is equal to 2**17 bits(1.048 ms.)
1 = Scrambler and descrambler functions bypassed.
0 = Normal Scrambler/Descrambler operation.
1 = 4B/5B encoder and 5B/4B decoder functions are bypassed.
0 = Normal 4B/5B and 5B/4B operation.
1= NRZI By pass(TX/RX).
0= Normal NRZI Operation(TX/RX).(default)
1 = 100Base-TX Loop Back.
0 = Normal TX/RX.(default)
The values of the ID[4:0] pins are latched into this register at power-up/
reset.
Preliminary Spec. ver
4
3
DHybrid
5
4
PHYAddr
1.4
11h
2
1
0
IDLESEL
12h
0
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