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Preliminary Spec. ver
1.4
KS8910 100/10 Mbps ETHERNET TRANSCEIVER
6
ANALOG BLOCKS
OVERVIEW
The 100Base-TX Analog block interfaces the digital logic to the transmit and receive twisted-pair interfaces. A block
diagram of the 100Mbit/s data path is shown in Figure 6-1. The 100Mbit/s digital components are described in
Chapter 4. The analog components are shaded and are described in this chapter.see figure 6-2 for the analog
block of the KS8910.
The main transmit analog blocks are the frequency synthesizer and the transmitter. The receive blocks include a
receive buffer, an adaptive equalizer, a baseline restore circuit, and clock recovery. In addition, the receive circuit
detects the presence of on the receive twisted pair and supplies status signals to the autonegotiation circuit
indicating lock detect and signal detect.
A few board-level passive components are required to support the analog circuits. These components include a 25
MHz crystal, a reference bias resistor, but the chip loop filters for the transmit and receive PLLs is integrated on
chip.
100Mbit/s Digital Blocks
100Mbit/s Analog Blocks
4B5B
MII
5B4B
25Mhz
Scrambler
Descrambler
Baseline Restore
Clock
Recovery
Figure 6-1. 100Mbit/s Data Path Block Diagram of KS8910
Frequency
Synthesizer
Transmitter
Adptive
Equalization
100BASE-TX ANALOG BLOCKS
Chip
Cat.5 UTP
Transformer
Cat.5 UTP
Board
6-1
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