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TC9462F(IC521):
1.Pin layout & Block Diagram
80
79
78
77
76
75
DV
81
SR
RO
82
1bit
LPF
DV
83
DAC
DD
DVR
84
LO
85
DV
86
SL
TEST1
87
TEST2
88
TEST3
89
BUS0
90
Micon
BUS1
91
interface
Correction
BUS2
92
BUS3
93
V
94
DD
V
95
SS
BUCK
96
CCE
97
Audio out
TEST4
98
TSMOD
99
circuit
RST
100
1
2
3
4
5
6
2.Pin function
PIN No.
SYMBOL
I/O
1
TEST0
I
2
O
HSO
3
UHSO
O
EMPH
O
4
LRCK
O
5
6
V
--
SS
BCK
7
O
AOUT
8
O
DOUT
9
O
MBOV
10
O
IPF
11
O
O
12
SBOK
I/O
13
CLCK
14
V
--
DD
15
V
--
SS
16
DATA
O
17
SFSY
O
18
SBSY
O
19
SPCK
O
20
SADA
O
21
COFS
O
22
MONIT
O
23
V
--
DD
24
TESIO0
I
25
P2V
--
REF
74
73
72
71
70
69
68
67
Clock
generator
Address circuit
circuit
16KRAM
Digital out
7
8
9
10
11
12
13
14
FUNCTIONAL DESCRIPTION
Test mode terminal.Normally, Keep at open.
Playback speed mode flag output terminal.
UHSO
HSO
PLAYBACK SPEED
H
H
Nomal
H
L
2 times
L
H
4 times
L
L
Subcode Q data emphasis flag output terminal.Emphasis ON at "H" level and OFF at "L"
level.The output polarity can invert by command.
Channel clock output terminal.(44.1khz)L-ch at "L" level and R-ch at "H" level. the output
polarity can invert by command.
Digital GND terminal.
Bit clock output terminal.(1.4112MHz)
Audio data output terminal.
Digital data output terminal.
Buffer memory over signal output terminal. Over at "H" level.
Correction flag output terminal. At "H" level,AOUT output is made to correction
impossibility by C
correction processing.
2
Subcode Q data CRCC check adjusting result output terminal.
The adjusting result is OK at "H" level.
Subcode P W data readout clock input/output terminal.
This terminal can select by command bit.
Digital power supply voltage terminal.
Digital GND terminal.
Subcode P W data output terminal.
Play-back frame sync signal output terminal.
Subcode block sync signal output terminal.
Processor status signal readout clock output terminal.
Processor status signal output terminal.
Correction frame clock output terminal. (7.35kHz)
Internal signal (DSP internal flag and PLL clock) output terminal.Selected by command.
This terminal output the text data with serial by command.
Digital power supply voltage terminal.
Test input/output terminal.Normally,keep at "L" level.
The terminal that inputted the clock for read of text data by command.
PLL double reference voltage supply terminal.
66
65
64
63
62
61
60
59
Servo
control
ROM
Digital equalizer
Automatic adjustment
RAM
circuit
CLV servo
Synchronous
guarantee
EFM decode
Sub code
decoder
Status
15
16
17
18
19
20
21
22
--
KD-SX975 / KD-SX875
58
57
56
55
54
53
52
51
PWM
D/A
+
-
+
A/D
-
+
-
Data
slicer
VCO
+
PLL
-
TMAX
23
24
25
26
27
28
29
30
REMARKS
With pull-up resistor.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
50 V
REF
49 TRO
48 FOO
47
TEZI
46 TEI
45 TSIN
44 SBAD
43 FEI
42 RFRP
41 RFZI
40 RFCT
39 AV
DD
38 RFI
37 SLCO
36 AV
SS
35 VCOF
34 VCOREF
33 PV
REF
32 LPFO
31 LPFN
1-27
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