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QQ
3 7 63 1515 0
SAA6579T-X(IC71):RDS
1.Pin layout
DATA
Vref
MUX
Vdd
GND
CIN
SOUT
2.Block diagram
4
8
7
5
3
TE
L 13942296513
3.Pin function
Pin No.
10
11
12
www
13
14
.
15
16
http://www.xiaoyu163.com
CLK
1
16
2
15
OSCO
3
14
OSCI
4
13
5
Vdd
12
GND
6
11
TEST
7
10
MODE
8
9
ANTI-
57 kHz
ALIASING
BAND PASS
FILTER
(8th ORDER)
COSTAS LOOP
CLOCKED
VARIABLE AND
COMPARATOR
FIXED DIVIDER
VP1
CLOCK
REFERENCE
REGERATION
VOLTAGE
AND SYNC
6
Symbol
1
No connect
2
DATA
RDS data output
3
Vref
Reference voltage output (0.5V
4
MUX
Multiplex signal input
5
Vdd
+5V supply voltage for analog part
6
GND
Ground for analog part (0V)
7
CIN
Sub carrier input to comparator
8
SOUT
Sub carrier output of reconstruction filter
9
MODE
Oscillator mode / test control input
TEST
Test enable input
GND
Ground for digital part (0V)
Vdd
+5V supply voltage for digital part
OSCI
Oscillator input
x
ao
y
OSCO
Oscillator output
i
No connect
CLK
RDS clock output
http://www.xiaoyu163.com
8
13
14
OSCILLATOR
RECONSTRUCTION
AND
FILTER
DIVIDER
BIPHASE
SYMBOL
DECODER
TEST LOGIC AND OUTPUT
SELECTOR SWITCH
Q Q
3
6 7
1 3
9
10
Description
u163
.
2 9
9 4
2 8
12
1
QUALITY BIT
GENERATOR
2
DIFFERENTIAL
DECODER
16
15
1 5
0 5
8
2 9
9 4
11
)
DDA
m
co
KS-FX732R
9 9
2 8
9 9
1-29
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