Table of Contents
Advertisement
KD-LH1150,KD-LH1100
4.15 TC94A14FA (IC621) : DSP & DAC
• Terminal layout & block daiagram
48
49
50
51
LPF
52
53
54
55
56
57
58
59
60
61
62
63
64
1
• Pin function
Pin
Symbol I/O
No
1
BCK
O
Bit clock output pin.32fs48fsor 64fs selectable by command.
2
LRCK
O
L/R channel clock output pin."L" for L channel and "H" for R channel.
Output polarity can be inverted by command.
3
AOUT
O
Audio data output pin. MSB-first or LSB-first selectable by command.
4
DOUT
O
Digital data output pin.Outputs up to double-speed playback.
5
IPF
O
Correction flag output pin. When set to "H" AOUT output cannot be corrected by C2 correction processing.
6
V
-
Digital 3.3V power supply voltage pin.
DD3
7
V
-
Digital GND pin.
SS3
8
SBOK
O
Subcode Q data CRCC result output pin. "H" level when result is OK.
9
CLCK
O
Subcode P-W data read I/O pin. I/O polarity selectable by command.
10
DATA
O
Subcode P-W data output pin.
11
SFSY
O
Playback frame sync signal output pin.
12
SBSY
O
Subcode block sync signal output pin. "H" level at S1 when subcode sync is detected.
13
HSO
I/O General-purpose input / output pins.Input port at reset.
14
UHSO
15
PV
-
PLL-only 3.3V power supply voltage pin.
DD3
16
PDO
O EFM and PLCK phase difference signal output pin.
1-42 (No.49817)
47
46
45
44
43
Clock
generator
1-bit
DAC
Address
circuit
RAM
Audio out
Digital
circuit
output
Micro-
controller
interface
2
3
4
5
6
42
41
40
39
38
PWM
Servo
control
ROM
Digital equalizer
automatic
RAM
adjustment circuit
CLV servo
16 k
Synchronous
guarantee
EFM
decoder
Sub code
decoder
7
8
9
10
11
Descroption
37
36
35
34
33
D/A
A/D
Data
slicer
VCO
PLL
TMAX
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Advertisement
Table of Contents
