Motorola LB3 (42.0 - 50.0MHz) Service Information page 14

2-8
for low frequency digital modulation, a balance attenuator to balance the high frequency analog
modulation and low frequency digital modulation, a 13V positive voltage multiplier, a serial interface
for control, and finally a super filter for the regulated 9.3 volt supply.
Regulated 9.3 volts DC applied to the super filter input (U1201 pin 30) delivers a very low noise
output voltage of 8.3 volts DC (VSF) at pin 28. External device Q1201 allows greater current
sourcing capability. The VSF source supplies the receive and transmit VCOs and first buffer stages.
The synthesizer IC supply voltage is provided by a dedicated 5V regulator (U1250) to minimize
power supply noise.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin
VCP (U1201 pin 47), a capacitive voltage multiplier circuit (CR1202 and C1209) generates a voltage
of 13 volts DC. This multiplier is driven by two 1.05 MHz clock signals from U1201 pins 15 and 14
(VMULT1 and VMULT2) which are 180° out of phase.
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
9,3V (U641 PIN 5)
5, 13, 20, 34, 36
+5V (U3211 PIN 1)
REFERENCE
OSCILLATOR
VOLTAGE
MULTIPLIER
Q1202
BUFFER
Output LOCK (U1201-4) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. A buffered output of the 16.8 MHz reference frequency is
provided at pin 19.
The operating frequency of the synthesizer is loaded serially from the microprocessor via the data
line (DATA, U1201-7), clock line (CLK, U1201-8) and chip select line (CSX, U1201-9).
The reference oscillator circuit within U1201 uses an external 16.8 MHz crystal (Y1201). Varactor
CR1201 allows software-controlled frequency adjustment (warp) and temperature compensation of
the oscillator frequency. Warp adjustment is performed using serial data from the microprocessor.
This controls the setting of an A/D converter, with its output (WARP, pin 25) applied to CR1201.
7
DATA
8
CLK
U1201
9
CEX
LOW VOLTAGE
10
MODIN
FRACTIONAL-N
30
SYNTHESIZER
SFIN
VDD, DC5V
23
XTAL1
24
XTAL2
25
WARP
32
PREIN
47
VCP
VMULT2 VMULT1
14
15
PRESCALER IN
Figure 2-3 LowBand Synthesizer Block Diagram
4
LOCK
19
FREFOUT
6, 22, 33, 44
GND
43
IOUT
45
IADAPT
41
MODOUT
3
AUX4
N.C.
1
AUX2
N.C.
2
AUX3
FILTERED 8,3V
28
SFOUT
BIAS1
40
AUX1 BIAS2
39
48
BWSELECT
THEORY OF OPERATION
LOCK (U0101 PIN 56)
FREF (U0221 PIN 34)
STEERING
LINE
2-POLE
LOOP
FILTER
VCTRL
LO RF INJECTION
VOLTAGE
CONTROLLED
OSCILLATOR
TX RF INJECTION
(1ST STAGE OF PA)