JVC KD-S733R Service Manual page 22
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Also See for KD-S733R:
- Instructions manual (106 pages) ,
- Installation & connection manual (4 pages) ,
- Instructions manual (32 pages)
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KD-S733R/KD-S731R
TC9462F (IC541) : DSP
1.Pin layout & Block Diagram
80
79
78
77
76
DV
81
SR
RO
82
1bit
LPF
DV
83
DD
DAC
DVR
84
LO
85
DV
86
SL
TEST1
87
TEST2
88
TEST3
89
BUS0
90
Micon
BUS1
91
interface
BUS2
92
BUS3
93
V
94
DD
V
95
SS
BUCK
96
CCE
97
Audio out
TEST4
98
TSMOD
99
RST
100
1
2
3
4
5
2.Pin function
PIN No.
SYMBOL
1
TEST0
2
HSO
3
UHSO
EMPH
4
LRCK
5
V
6
SS
BCK
7
8
AOUT
DOUT
9
10
MBOV
IPF
11
12
SBOK
13
CLCK
14
V
DD
15
V
SS
16
DATA
17
SFSY
18
SBSY
19
SPCK
20
SADA
21
COFS
22
MONIT
23
V
DD
24
TESIO0
25
P2V
REF
1-22
75
74
73
72
71
70
69
68
Clock
generator
Address circuit
Correction
circuit
16KRAM
Digital out
circuit
6
7
8
9
10
11
12
13
FUNCTIONAL DESCRIPTION
I/O
I
Test mode terminal.Normally, Keep at open.
Playback speed mode flag output terminal.
UHSO
HSO
PLAYBACK SPEED
O
H
H
H
L
L
H
L
L
O
Subcode Q data emphasis flag output terminal.Emphasis ON at "H" level and OFF at "L"
O
level.The output polarity can invert by command.
Channel clock output terminal.(44.1khz)L-ch at "L" level and R-ch at "H" level. the output
O
polarity can invert by command.
Digital GND terminal.
--
O
Bit clock output terminal.(1.4112MHz)
Audio data output terminal.
O
Digital data output terminal.
O
O
Buffer memory over signal output terminal. Over at "H" level.
Correction flag output terminal. At "H" level,AOUT output is made to correction
O
impossibility by C
correction processing.
2
Subcode Q data CRCC check adjusting result output terminal.
O
The adjusting result is OK at "H" level.
Subcode P W data readout clock input/output terminal.
I/O
This terminal can select by command bit.
--
Digital power supply voltage terminal.
--
Digital GND terminal.
O
Subcode P W data output terminal.
O
Play-back frame sync signal output terminal.
O
Subcode block sync signal output terminal.
O
Processor status signal readout clock output terminal.
O
Processor status signal output terminal.
O
Correction frame clock output terminal. (7.35kHz)
Internal signal (DSP internal flag and PLL clock) output terminal.Selected by command.
O
This terminal output the text data with serial by command.
--
Digital power supply voltage terminal.
Test input/output terminal.Normally,keep at "L" level.
I
The terminal that inputted the clock for read of text data by command.
--
PLL double reference voltage supply terminal.
67
66
65
64
63
62
61
60
Servo
control
ROM
Digital equalizer
Automatic adjustment
RAM
circuit
CLV servo
Synchronous
guarantee
EFM decode
Sub code
decoder
Status
14
15
16
17
18
19
20
21
Nomal
2 times
4 times
--
59
58
57
56
55
54
53
52
PWM
D/A
+
-
+
A/D
-
+
-
Data
slicer
VCO
+
PLL
-
TMAX
22
23
24
25
26
27
28
29
REMARKS
With pull-up resistor.
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
51
50 V
REF
49 TRO
48 FOO
47
TEZI
46 TEI
45 TSIN
44 SBAD
43 FEI
42 RFRP
41 RFZI
40 RFCT
39 AV
DD
38 RFI
37 SLCO
36 AV
SS
35 VCOF
34 VCOREF
33 PV
REF
32 LPFO
31 LPFN
30
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