EAI TR-20 Operator's Reference Manual page 40

30
x
+
+IOA
+A
0 S
B
B 0 0
+
y
-lOS AS +10
+B
-B
0< B S +10
IBI>
I
A
I
Figure
12.
Division Circuit for a Quarter-Square Multiplier
-INa
So
°0;
R~
+INO
So
°0
x 2 DFG
16.101
1---1
X2DF~
-INPUTS
...--t
R51
J\ A A
3550
2
50
~
R5
~
35
x
2
DF~;>--
+INPUTS
R53
AAA
vv"
3550
Q.
SIMPLIFIED DIAGRAM
OF UNIT
X -IN
X 2
DFG
-IN
X
5
+X2
10
0
R~
+IN
X 2
y
DFG
y
+IN
5
_y2
10
0
X2 DFG
-IOV
S
X
S
°
16.101
+IOV~y~O
b. TYPICAL PATCHIN G
c.
SYMBOLS
Figure
13.
r
DFG Patching
-lOA
-
B
10
_y2
10