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When the computer is placed in the reset mode, relay voltage is present on the reset
bus.
If the indicated patching connection in the RS area is made, K2 is energized,
and its contact moves to the alternate position shown.
This allows a voltage at the
IC terminal to be coupled through a 10K input resistor to the base of the ampli-
fier.
The feedback capacitor is now shunted by a 10K resistor.
This allows the
amplifier to perform as a unity-gain inverter (for the initial condition voltage)
with a time lag of approximately 0.5 seconds.
For this reason, the computer should
always be left in the reset mode for at least one-half second before switching to
the hold or operate modes, to assure that the correct initial condition potentials
are established.
When the computer is switched to the operate mode, K2 de-energizes and Kl energizes.
This applies the input potentials at the SJ terminal of the network to the base of
the amplifier.
Since K2 is de-energized, the capacitor provides the only feedback
path for the amplifier, and integration with respect to time takes place.
.
The patching connections in the cross-hatched area have been indicated for stand-
ard operation.
For special situations, these connections may be different.
For
example, if the RS connection is deleted, the integrator cannot be placed in the
reset mode; remaining in hold when the other integrators in the computer are being
reset.
This allows the value reached during a solution to be used as an initial
condition for the next solution.
Patching and a brief description of these
spe~ial
situations is provided in the appendix.
(2)
Integrator Network 12.1115.
This network differs from
th~
network pre-
viously described principally by providing two values of feedback capacitor.
These
values (10 mfd and 0.02 mfd) allow a 500 to 1 change in time scale.
Figure 10
illustrates the patching connection and the circuit arrangement of the network.
Note that the patching connections to the amplifier are identical to those for
a 12.1116 Network.
An additional patching connection is required on the integrator
network in the cross-hatched area designated SPEC, if the integrator is to be used
in the standard rep-op mode.
The Operate and Reset relays (Kl and K2 of Figure 9) have been replaced by a single
balanced-armature relay (K3 of Figure 10).
This allows the integrator to be switched
between operate and reset modes very rapidly, a necessary requirement for repetitive
operation.
Relay Kl selects the correct value of feedback capacitance for normal
or repetitive operation.
If the connection in the SPEC area is delected, the inte-
grator has a feedback capacitance of 10 mfd for either mode.
T~is
patching is de-
scribed in the appendix.
Relay K2 grounds the SJ input during the reset and hold modes.
The relay is ener-
gized during the operate and rep-op modes, through CRl or CR2 respectively.
When
K2 is energized, the SJ input is connected to the operate contact of the Repetitive
Operation relay (K3).
Therefore, when a problem is being set up on a computer
equipped with the 12.1115 Networks, the Mode Control switch must be placed in the
RESET position and the COMPUTE TIME MILLISEC switch must be placed· in the OFF
position.
24
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