Yamaha RX-V595 Service Manual page 54

A B
RX-V595/R-V905/RX-V595RDS
SCHEMATIC DIAGRAM (TUNER) B, G models
1
2
10.3 10.4
(0) (11.6)
3
0.1
(10.6)
VT
87.5MHz 1.7V
FM 98.1MHz 4.1V
108.0MHz 8.3V
531KHz 1.4V
1080KHz 5.1V
AM
1611KHz 7.4V
4
bottom view
5
6
7
8
PIN CONNECTION DIAGRAM OF DIODES, TRANSISTORS AND IC's.
1SS133 2SC1740S(R,S) 2SC535(A, B,G) LA3401
1SS176 DTA114ES 2SC1815(Y) LC72131
DTC144ES
HSS104
MTJ5-6B
Anode
B
C
Cathode E
63
C D
E
Each voltage given here repressents that in the FM (98.1MHz STEREO) reception mode
but the one in the parentheses ( ) is that in the AM (1080kHz, MAN'L) reception mode.
DISCRIMINATOR BALANCE ADJ.
AM/FM IF
MONAURAL DISTORTION ADJ.
FM
11.0
9.4 (11.2)
(9.4)
2.5
7.6 3.1
(2.1)
(2.8)
(7.5)
5.0 5.1
(5.1)
(5.1)
4.3
(4.3)
AM AM SENSITIVITY ADJ.
SIGNAL METER ADJ.
0
(9.4)
11.5
(0.2)
11.5
(11.6)
0
(2.4) (0)
0
(4.5) 0.5 0.1 (10.6)
0 (0)
REGULATOR
0 (0)
(2.4) 0
(0)
2.4 11.5 (0.2)
(4.9) 4.9
0 (0) 4.9 11.5
(1.0)1.1 (4.9) (11.6)
0 (0)
(1.0)1.1 0 (0)
5.6
(5.1) 4.1 0 (0) (5.6)
(0) 0
2.4 (2.4)
(2.5) 2.5
5.6
(5.6)
1 0
(0)
PLL
Point 1 (Pin22 of IC2)
V : 2V/div H : 50nsec/div DC range
LA1266
LC72720N
0V
12
24
SAMPLE 50us
2V 2V
G
F
MPX
FM
0
(0)
0 2.8 2.8
(0) (9.2)
(9.2)
AM
0 (0)
4.9
(4.9)
0 (0)
SEPARATION ADJ.
RDS DECODER
2
Point 2 (Pin12 of IC4)
V : 2V/div H : 0.1µsec/div DC range 1 : 1 probe
1 : 1 probe
0V
2V SAMPLE 0.1us
H I J
IC1 : LA1266
AM/FM IF
IC2 : LC72131
PLL Controller
IC3 : LA3401
MPX
TO INPUT(1) IC4 : LC72720N
CB107
RDS Decoder
P58 H-8
VDDA 3
VSSA
4
MPX IN 2
DO 20
CL
21
DI 22
CE 23
T1 7
T2
8
T3 9
T4
10
• PK1 : ENV-172A4G1 (V2716700)
C1 C11
39P 22P
R1
L9
100K
C28
6P
C32
0.01µ
1 2 3
All voltages are measured with a 10M Ω /V DC electric volt meter.
Components having special characteristics are marked
must be replaced with parts having specifications equal to those
originally installed.
Schematic diagram is subject to change without notice.
K L
1 5 6
CLOCK
+ 14 VDDD
PLL
RECOVERY
REFERENCE (57kHz)
(1187.5Hz)
VOLTAGE
15 VSSD
VREF
57kHz
DATA
ANTIALIASING SMOOTHING
bpf 19 RDS-ID
FILTER FILTER DECODER
(SCF)
18 SYNC
RAM ERROR CORRECTION SYNC/EC
CCB (24 BLOCK DATA) (SOFT DECISION) CONTROLLER
24 SYR
CLK(4.332MHz)
MEMORY
CONTROL
TEST SYNC SYNC
DETECT-1 DETECT-2
OSC/DIVIDER
11 16 17 13 12
Q2
C8
2SC535 L7
L1 4P
DT2 DT3
SVC212 SVC212
Q1 R4
C3 C5
2SK439 150
0.75P 10P
L5
R19
R26 L4
0.47m
1.5K
L2 L3
DT1 R8
SVC212 10K
C24
C6 C7
47P
C2 C4 R3 7P 2.5P
15P 7P 100K C10 R7
R27 27P 1M
390
R2 C30 C13 R5 R6
C31 C9
L8
100K 0.01µ 0.018m 0.018m 100K 100K 470P
R9
33
R20 R21
C29 C27 R12 R22 R23
330K 470
2P 0.018m
10K 330K 330
Q4
Q5
2SC461 2SC461
C16 C17 C19
2P 8P 5P
R10
4.7K
C18
27P
R24
R25
C15 L6 10
Q6
C26 C12 C25 C14 DT4 R13 R14 C20 C23
2SC461
0.01µ 0.018µ 0.01µ 47P 10K 1.8K 12P 15P
SVC212
4 5 6 7 8
and