Aiwa AM-HX70 Service Manual page 14

IC DESCRIPTION
IC, CXD2665GA
Pin No. Circuit Pin No.
A-1 –
A-2 –
A-3 3
B-1 –
B-2 –
B-3 2
C-1 5
C-2 4
C-3 –
D-1 7
D-2 6
D-3 1
E-1 8
E-2 10
E-3 11
F-1 9
F-2 13
F-3 12
G-1 14
G-2 16
G-3 15
H-1 17
H-2 19
H-3 18
J-1 20
J-2 –
J-3 –
K-1 21
K-2 24
K-3 25
L-1 22
L-2 23
L-3 26
M-1 29
M-2 27
M-3 28
N-1 30
N-2 31
Pin Name I/O
NC – Not connected.
NC – Not connected.
MNT1 O Monitor output.
NC – Not connected.
NC – Not connected.
MNT0 I/O Monitor input/output.
MNT3 O Monitor output.
MNT2 O Monitor output.
NC – Not connected.
SCLK I Microprocessor serial bus clock input.
SWDT I Microprocessor serial bus data writing input.
VDC0 – VDD for internal logic (1.8V).
XLAT I Microprocessor serial bus latch input.
SRDT O Microprocessor serial bus data reading output.
SENS O Internal state output to the microprocessor serial bus address.
VSC0 – GND for internal logic.
ADIP synch output when PTGR (ADRS = $3B, DATA1 - D7) = 0.
SQSY O
DISC SUB-Q synch output when PTGR = 1.
XRST I Reset input. Reset with "L".
MTFLGL O Lch zero data detection flag output (Not used).
XINT O Interruption status output. "L" at interruption status.
TST1 I Test pin. Set to "L".
TST2 I Test pin. Set to "L".
OSCI I X'tal oscillation circuit input (OSCI pin reverse output).
VDIOSC – VDD for OSC cell (2.4V).
OSCO O X'tal oscillation circuit output.
NC – Not connected.
NC – Not connected.
VSIOSC – GND for OSC cell.
AOUTL O Built-in DAC Lch output.
DAV L – VDD for built-in DAC (Lch 2.4V).
DD
DAV L – GND for built-in DAC (Lch).
SS
Built-in DAC VREF (Lch).
VREFL O
(Connect to GND via a capacitor of approximately 1µ F).
DAV R – VDD for built-in DAC (Rch 2.4V).
DD
DAV R – GND for built-in DAC (Rch).
SS
AOUTR O Internal DAC Rch output.
Built-in DAC VREF (Rch) .
VREFR O
(Connect to GND via a capacitor of approximately 1µ F).
VSC1 – GND for internal logic.
XTSL I Swith input frequency of OSCI pin.(Connected to VDD)
Description
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