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HCD-EP50LIV
Q Q
3 7 6 3 1 5 1 5 0
• Waveforms
– MAIN Board –
1 U2 w; (X2)
4 Q31 (Base) (REC (ISS 1) mode)
2.4 Vp-p
13.5 µs
139 ns
2 Q41 (Collector) (REC (ISS 1) mode)
4 Q31 (Base) (REC (ISS 2) mode)
7 Vp-p
13.5 µs
12.5 µs
2 Q41 (Collector) (REC (ISS 2) mode)
5 Q31 (Emitter) (REC (ISS 1) mode)
T E
L
1 3 9 4 2 2 9 6 5 1 3
110 Vp-p
12.5 µs
13.5 µs
3 Q31 (Collector) (REC (ISS 1) mode)
5 Q31 (Emitter) (REC (ISS 2) mode)
10 Vp-p
13.5 µs
12.5 µs
3 Q31 (Collector) (REC (ISS 2) mode)
w w w
10 Vp-p
12.5 µs
– DISPLAY Board –
1 IC301 7 (X2)
3.1 Vp-p
238 ns
3.1 Vp-p
620 mVp-p
620 mVp-p
x
a o
y
.
i
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8
• IC Block Diagrams
– MAIN Board –
U1 LA1837L
30
29
28
27
26
25
5.1 Vp-p
REG
ALC
AM
AM
AM
OSC
MIX
RF. AMP
BUFF
AGC
SD
COMP
AM
DET
IF
AM
AM/FM
S-METER
IF-
FM
S-CURVE
BUFF
S-METER
TUNING
DRIVE
FM
FM
IF
DET
GND
1
2 3
4
5
U2 LC72131M-TL-M
Q
Q
3
7
6
3
20
19
18
17
16
PHASE
DETECTOR
CHARGE PUMP
REFERENCE
UNLOCK
DIVIDER
DETECTOR
SWALLOW COUNTER
1/16, 1/17 4BITS
PROGRAMMABLE
CCB
DATA SHIFT REGISTER LATCH
INTERFACE
1
2 3 4 5
u 1 6 3
.
28
28
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2
4
9
9
24
23
22
21
20
19
18
17 16
DECODER
ANT 1-BIRDIE
STEREO
SW
STEREO
DRIVE
MUTE
FF
FF
FF
VCO
PILOT
DET
PHASE
DET
VCC
12
13
6
7
8
9
10
11
14
15
1
5
1
5
0
8
9
2
15
14
13
12
11
POWER
1/2
ON
RESET
12BITS
DRIVER
UNIVERSAL
COUNTER
6 7 8 9
10
m
c o
2
8
9
9
4
9
8
2
9
9

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