Roland TR-808 Service Notes page 4

TR-808
JUN.15,1981
CPU PI-1_
Memory CE
lO^S
lOjULS
lO^s
VALib ADbRESB
READ CYCLE
IC7-IC10
pins 11-14
PC 0-3
Data read
STORED
DATA]
1
2
3
RAM,
Address Decoder
Four
static
CMOS
RAMs
(juPD444C,
IK
x
4-bit) are
used for
memory.
The
memory map
is
shown
in Fig. 4.
The upper two
bits
PE2
and
PE3
of
CPU
designate
a
RAM,
IC5
decodes
these bits,
and
the
memory
select
is
enabled
by
a
signal
from
PI-1
(CE). See
Fig. 5.
Cell addresses are designtated by bits
from PD, PE and
PF. After
'lOfj.s
of CE, the data
shown
in Fig.
5-2
is
read
(5-3)
or
a
new
data from
PC
is
written (Fig. 5-5).
As can be seen from
Fig.
5-2 and
-4,
during
writing,
PC output
data
and
RAM
data
at
the I/O ports of
RAM
may
conflict with
one
another.
To
prevent
this,
the buffer
resistors
(R85—
R88) are
con-
nected.
The
LED
driver transistors
(Q2-Q5)
for
BASIC VARIATION, 1ST
and
2ND
are directly
connected
to the
bus of PD and PE. However,
since various data appear on the bus by time sharing processing, the
LEDs may sometimes
light
even when
unnecessary signals are applied,
resulting in
possible
lighting
timing
disparity in a
mode.
RAMs'
low power consumption during high
CE
allows memories to
be maintained for longer period with back-up battery.
Trigger
Gate
Pulses corresponding to the shortest rhythm
step usable
by TR-808
are
fed from
PI-2 of
CPU
at
a
time
interval determined by the setting
of
TEMPO CONTROL
(Fig. 6-1).
On
the other hand, instrument
data to be reproduced
are applied
from PD, PE and PF
to the gate
of each
sound
generator
in
synchronization with
step pulses (Fig. 6-3).
Since the step pulse width
of 10)Us
is
too
narrow
to trigger
a
sound
generator,
it is
widened
to approx.
1ms
which
is
nearly equal to the
width of instrument data
signal. This
widening
is
accomplished by
the monostable
IC6.
It is
triggered by
a rising
edge of 027-inverted
pulse. (Fig. 6-2).
The
L period
is
determined by
the
sum
of the
time constants of R
1
00 x C23 and R
1
02 x C27.
The
output from
pin
10 of ICO
passes
through
the
ACCENT
circuit
composed
of
Q31—
Q34, becomes
a
COMMON
TRIG
signal,
and
simultaneously applied to the
gates of
all
sound
generators
in
parallel.
When
instrument data
is
present
at a gate, this trigger signal
is
ANDed
with the data and
activates the corresponding
sound
generator (See
Fig. 7).
Since the
AND
output
from
the gate
is
in
proportion to the amplitude
of the
common
trig signal, the output of the sound generator has the
amplitude
in
proportion
to
the
common
trig signal. Accordingly,
when
ACCENT
data are present, they
are
added to the
common
trig
signal.
Since the output
of pin 10 of IC6
is a
negative logic signal,
when
there are no step
pulses,
the output
signal
becomes
H,
Q31
turns on and
places a
ground
at base of Q32.
When
pin 10 of IC6
becomes
L,
Q31 becomes
off,
and when
ACCENT
data
from PF-3
is
L
(no accent),
Q34
turns on to shunt
VR3.
As
a result,
the base of
Q32
becomes approx.
-i-5V
and
trig
amplitude
is
approx. 4V.
When
ACCENT
data
is
H,
a
voltage between
5V
and
15V
according to
VR3
setting
is
applied to the base of Q32, and
is
converted into
trig
pulses
of approx.
4—
14V.
This explains that
ACCENT
level
can be changed
by
VR3.
In the case of CB, CY,
OH
and CH,
trig variation range
is
narrowed
to
7V—
14V by
1/2
IC2
(pins
1—3) on
the voicing board to increase
S/N
ratio.
STELE
FIGURE
6
INSTRUMENT
TRIG-INSTRUMENT
DATA
TIMING
DATA
WRIT^ CYCLE
4
FIGURE
7
VOICE
GENERATOR TRIGGER
PULSE
FIGURE
5
READ/WRITE CYCLE TIMING
4