Roland TR-808 Service Notes page 3

TR-808
JUN.
15,
1981
TR-808 CIRCUIT DESCRIPTION
FIGURE
1
BLOCK DIAGRAM
MPD650C-085 FUNCTIONAL DESCRIPTION
No,
PH
0
(PortH)
1
2
3
26
27
28
29
Scanning signal outputs to switches
Switching signal outputs to
STATUS BUFFER & GATE
PA
0
(Port A)
1
2
3
33
34
35
36
Switch
scanning signal inputs
STATUS
(TEMPO. CLOCK. START/STOP. FILL
IN) inputs
PB 0
(Port B)
1
2
3
37
38
39
40
Inputs
from STEP
Switches
(RHYTHM SELECT
Swtiches)
PG 0
(PortG)
1
2
3
22
23
24
25
Drive signals to
STEP LEDs
PE
0
(Port E)
1
2
3
12
13
14
15
1st/2nd CP
A/B RS
Memory
bank
HT
select
MT
MEMORY ADDRESSES
CH
INSTRUMENT DATA
p.
.
These
pins use
CE from qu These
data
need
n^umbeTs
ADDRESS
Decoder
to
^
COMMON
TRIG
to
select cells in
RAM
to trigger
Sound Generators
be accessed
CB
being designated
LT
Step
SD
numbers BD
AC
PD
0
(Port D)
1
2
3
8
9
10
11
PF 0
(Port F)
1
2
3
16
17
18
19
PC
0
(Port C)
1
2
3
2
3
4
5
Data Inputs/Outputs
PI
0
(PortI)
1
2
30
31
32
Memory
WE
Memory CE
(associated
with PE-2, 3
at
ADDRESS DECODER)
Trigger Pulse
(INSTRUMENT) output
General
As
can be seen
from
the block diagram,
most
processes of
TR-808
up
to generation of pulses
triggering
sound generators
are
controlled by
the computer.
CPU
pin functions are
as
shown
at the lower
left
table.
Once power
is
turned on for TR-808,
pulses are generated
from
PI-2
of
CPU
regardless of
TR-808
function
mode
(Start/Stop) and of
presence or absence of rhythm
patterns.
The time
length
between
the pulses
is
equal to that of the shortest
rhythm
patterns. The pulse
is
transfered to
TRIGGER MONO,
then
ACCENT
from which
it is
applied
in
parallel to
ail
the gates prestaged to Sound Generators;
accordingly,
called
COMMON
TRIGGER. On
the other hand, instru-
ment
data designating sound to be outputted
are
independently
supplied to the
gates
from
corresponding exclusive ports (PD,
PE
and PF). Since Instrument data
are
time
sharing the data buss
with
memory
addresses, the data are aligned with
Common
Trigs
in
timing.
When
these two
signals are applied, the gate
ANDs
the
two
signals
and
outputs a signal triggering the sound generator. Since the peak
value
of this trig signal
is
in proportion to that of the
Common
Trig pulses,
when
an accent data
is
outputted, the data
can be used
to
change
the amplitude of the
Common
Trig signal.
Panel control
settings are read
by
interruption of
CPU
each time
an interrupt
signal is
fed to the
INT
terminal.
First,
the Buffer
&
gate turns on by
a signal
from PH, and
the status
is
read
through PA.
Then, some
statuses of function switches
are
read through
PA
by
a signal
from one port of PH. At
the
same
time,
some
statuses of
a
group
of step switches are read through PB, and the step
LED
drive
signal
is
outputted from
PG
as required. Statuses are read each time an
INT
signal
is
fed. However, statuses of the step and function switches
are
read every four times of INT
signals.
Four
CMOS
RAMs
(IK x
4-bit) are
used
for data storage.
Chips
are
selected
when
the
upper two
bits
of
PE
data decoded by IC5 are
enabled by pulses from
PI-1.
Addresses of chip
memory
cells are
designated
by
bits of
PD, PE and
PF. Data storage to addresses are
possible
when
an L output from
PI-0
is
applied to
WE
.
Detail
SW
Scanning, Status Reading
Reading of statuses of the
controls
on the panel
(step switches,
function switches,
tempo,
etc.) starts
when
an interrupt
signal is
applied to INT terminal every 1.9ms.
When
the signal
is
applied to
INT
terminal,
CPU
starts
interruption.
The
interruption period
is
approx.
600/us.
During
the first 150/us,
PHO—
PH3 become
H,
and
the collector of
AND
gate
Q18
becomes
L.
STATUS
signals are
ANDed
with this
L by ICS and
read through PA. After
150jus,
only
PH-0 becomes
L.
This
signal
is
converted
to
H by Q23, and
reaches
PB and
PA
through the closed contacts of the Step switches (No.
1
—
No.
4),
SWla
(Mode) and
SW2
(Clear).
When
one
of the four Step
switches
is
closed, the corresponding
STEP LED
lighting signal is
immediately fed from PG. Since the PG output
is
latched until the
next INT
signal
is
applied, the lighting period
is
approx. 1.8ms. This
period b
is
approx.
450/us.
The remaining
period c
is
for processing
of
main program. When
the next
INT
signal
is
applied,
PHO— PH3
become H
again,
the
statuses of
the
TEMPO CLOCK, START/STOP,
TAP,
etc. are read again.
Then, only PHI becomes
L and the statuses
of switches connected to the collector of
024
are read.
At the next
INT
signal,
STATUS
and PH2 become
L. Next,
PH3 becomes
L.
This change
is
repeated.
In this
way
statuses are checked each time an
INT
signal
is
applied every
1.9ms
so that the
CPU
can respond to the
status change promptly.
The
statuses of other switches
are
read every
four times of INT
signals. This
corresponds
to
one
reading every
7.6ms.
INTERRUPT
CLOCK
ICl pin
6
1
.
9ms
PHO
PHo
7
.
6ms
PHI
pin
26
PH2
PH3
150us
STATUS
gate
active low
STEP
1-4
MODE
CLEAR
STEP 5-8
PRESCALE
BASIC
VARI,
STEP 9-12
INSTR. SELECT
INSTRUMENT
SELECT
STEP 13-16
AUTO FILL
IN
I/P
VARIATION
TEMPO CLOCK
START/STOP
TAP
FIGURE
2
INTERRUPT CYCLE
TIMING DIAGRAM
INTERRUPT
CLOCK
PH
600us
1
a b
1
I
450/u.s
STATUS
GATE
All time lengths
are approximate.
15QU.S
3