Roland TR-808 Service Notes page 2

Hide thumbs Also See for TR-808:
Table of Contents

Advertisement

TR-808
JUN.
15,
1981
(Top View)
pPDAAAC
As
1
18
As
c
2
17
3
16
Aa
1
4
15
Ao
1
5
14
A,
c
6
13
A2
7
12
CS
8
11
GND
9
10
HM4334P-4
1
024
-word
X
4
-bit
Static
CMOS RAM
As
Ah
Ab
A:
As
I
Oi
I
02
I
03
I
04
cs
\VE
,mmm
c
-
+
~V0
IN
0-^V
U®U
© i
n
n n n riryf
I
^
W
[
/
IJ
U
Li
Jli
LJ'ir^
<7L
MC14001BCP
Quad
2-Input
NOR
Gate
TA7179P
DUAL
±15V
TRACKING
RAGULATOR
GND
BALANCE
+
COMPEN
+
SENSE
+
VOUT
NG
VCC
VOLTAGE
ADJUST
NC
-
COMPEN
-
SENSE
-
VOUT
NC
VEE
Heg.IN
=
5raV(
typ)
(
VIN=18-30Vj
Reg. OUT= 5mV
(
typ)
(
I0lJT=0-50raA}
Ripple rejection ratio
=
75dB
Output current
=
100mA
(max)
n-T
f
OUTPUT
COMMON
INPUT
ORDER
INFORMATION
OUTPUT
VOLTAGE
5
V
6
V
8
V
8.5
V
12
V
15
V
18
V
24
V
TYPE
44A7805C
MA7806C
MA7808C
MA7885C
MA7812C
mA7815C
mA7818C
mA7824C
PART
NO.
MA7805UC
31A7806UC
MA7808UC
44A7885UC
MA7812UC
MA7815UC
44A7818UC
^A7824UC
HA7800
SERIES
3-TERMINAL
POSITIVE
VOLTAGE
REGULATORS
ABSOLUTE
MAXIMUM
RATINGS
Input Voltage
(5
V
through 18
V)
(24
V)
Internal
Power
Dissipation
Storage
Temperature Range
Operating Junction
Temperature
Range
4iA7800
/4A7800C
Lead Temperature
(Soldering,
60
s
time
limit)
TO-3
Package
(Soldering,
10
s
time
limit)
TO-220
Package
35
V
40
V
Internally
Limited
-65°C
to
+150°C
-55°C
to
+150°C
0"C
to
+150°C
300°
C
230°C
HD14584B
MC14051B
8-Channel Analog
Hex
Schmitt
Trigger
Multiplexer/Oemultiplexer
Vdd
'
Pin 16
Vss
=
Pin
8
Vg
g
-
Pin 7
AN69I2
Quad
Comparator
0UTPUT2|T
OLFTPUTl
H
V-[3
TRUTH TABLE
1
Control Inputs
ON
Switches
Select
Inhibit
c
B
A MC14051B
MC14062B
MC14053B
0
0
0
0
xo
YO
XO
ZO
YO
XO
0
0
0
X
1
Y1
XI
zo
YO
XI
0
0
1
0
X2
Y2
X2
ZO
Y1
XO
0
0
1
1
X3
Y3
X3
zo
Y1
XI
0
1
0
0
X4
Z1
YO
XO
0
1
0
1
X5
Z1
YO
XI
0
1
1
0
X6
Z1
Y1
XO
0
1
1
1
X7
Z1
VI
X
1
1
X
X
X
None
None
c
0
2
'Not
applicable
for
MC14052
X
=
Don't Care
MC14051B
FUNCTIONAL
DIAGRAM
BLOCK
DIAGRAM
MC14013B
BA662
CJiD
/•£xUinnjQjm
CWT
)
llj'ilj
l!i
LlL ITtT
y
-<JV
TC4011BP
Quad
2-Input
NAND
Gate
IN
+
o
n n n
n.
)
LC
OTJ4
IN
^
/^PC 4558
C
DUAL
TYPE
D
FLIP-FLOP
TRUTH TABLE
Vdd
'
Pin
14
Vss
"
Pin
7
INPUTS
OUTPUTS
CLOCK*
DATA
RESET
SET
Q
Q
0
0
0
0
1
_r~
1
0
0
1
0
X
0
0
Q
Q
X
X
1
0
0
1
X
X
0
1
1
0
X
X
1
1
1
1
X
-
Don't Care
T
=
Level
Change
2

Advertisement

Table of Contents
loading

Table of Contents