JVC XV-S40BK Service Manual page 40

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XV-S40BK/XV-S42SL/XV-E100SL
3.Pin function (2/3)
Symbol
Pin No.
51
CPUADR5
52
CPUADR4
53
CPUADR3
54
CPUADR2
55
CPUADR1
56
VSS
57
CPUADR0
58
NCS
59
NWR
60
NRD
61
VDD
62
CPUDT7
63
CPUDT6
64
PVPPDRAM
65
PTESTDRAM
66
PVDDDRAM
67
PVSSDRAM
68
CPUDT5
69
CPUDT4
70
CPUDT3
71
VSS
72
CPUDT2
73
CPUDT1
74
CPUDT0
75
CLKOUT1
76
VDD
77
TEHLD
78
DTRD
79
IDGT
80
BDO
81
CPDET2
82
CPDET1
83
VSS
84
MMOD
85
NRST
86
VDD
87
CLKOUT2
88
SBCK/PLLOK
89
IDOHOLD
90
JMPINH
91
LG
92
NTRON
93
DACDATA
94
DACLRCK
95
DACCLK
96
IPFLAG
97
BLKCK
98
LRCK
99
VSS
100
OSCI1
1-28
I/O
I
System control address
I
System control address
I
System control address
I
System control address
I
System control address
-
Connect to GND
I
System control address
I
System control chip select
I
Writing system control
I
Reading system control
-
Power supply 3V
I/O
System control data
I/O
System control data
O
Connect to VSS
I
Connect to VSS
Connect to VDD(2.7V)
Connect to VSS
I/O
System control data
I/O
System control data
I/O
System control data
-
Connect to GND
I/O
System control data
I/O
System control data
I/O
System control data
O
Clock signal output (16.9/11.2/8.45MHz)
-
Power supply 3V
O
Mirror gate (Connect to TP141)
O
Data frequency control switch (Connect to TP304)
O
CAPA switch
I
RF Dropout/BCA data
I
Outer capacity detection
I
Inner capacity detection
-
Connect to GND
I
Connect to VSS
I
System reset
-
Power supply 3V
O
Clock 16.9MHz
O
Flame mark detection
O
ID gate for tracking holding
O
Jump prohibition
O
Land/group switch
I
Tracking ON
O
Serial data output (Connect to TP148)
O
Identification signal of L and R (Connect to TP149)
I
Clock for serial data output
I
Input of IP flag
I
Sub code/block/input clock
I
Identification signal of L and R (Connect to VSS)
-
Connect to GND
I
Oscillation input terminal 16.9MHz
Description

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