Vocoder Memory Map - Motorola ASTRO Digital Saber Service Manual

Vocoder Memory
Map
The SLIC is controlled through sixteen registers mapped into the MCU
memory at $1400 - $14FF. This mapping is achieved by the following
signals from the MCU: R/W*, CSIO1*, HA0-HA4,HA8, HA9. Upon
power-up, the MCU configures the SLIC including the memory map
by writing to these registers.
The SLIC memory management functions in conjunction with the
chip selects provided by the MCU provide the decoding logic for the
memory map which is dependent upon the "map" selected in the
SLIC. The MCU provides a chip select, CSGEN*, which decodes the
valid range for the external SRAM. In addition CSI01* and CSPROG*
are provide to the SLIC decoding logic for the external EEPROM and
FLASH ROM respectively. The SLIC provides a chip select and banking
scheme for the EEPROM and FLASH ROM. The FLASH ROM is banked
into the map in 16KB blocks with one 32KB common ROM block. The
external EEPROM may be swapped into one of the banked ROM areas.
This is all controlled by EE1CS*, ROM1CS*, ROM2CS*, HA14_OUT,
HA15_OUT, HA16, and HA17 from the SLIC (U206) and D0-D8 and
A0-16 from the MCU (U204).
The SLIC provides three peripheral chip selects; XTSC1B, XTCS2B, and
XTCS3B. These can be configure to drive an external chip select when
it's range of memory is addressed. XTSC1B is used to address the host
port interface to the DSP. XTSC2B is used to address a small portion of
external SRAM through the gate U211. XTSCB3 is used as general
purpose I/O for interrupting the secure module.
In bootstrap mode the memory map is slightly different. Internal
EEPROM is mapped at $Fe00-$FFFF and F1 internal SRAM starts at
$0000-$03fff. In addition a special bootstrap ROM appears in the ROM
space from $B600-$BFFF. For additional information on bootstrap
mode refer to the section Controller Bootstrap and Asynchronous
Buses.
The vocoder (DSP) external bus consists of three 8k x 24 SRAMs (U402,
U403, U414), one 256k x 8 FLASH ROM (U404), and ADSIC (U406)
configuration registers.
The DSP56001 (U405) has a 24 bit wide data bus (D0-D23) and a 16 bit
wide address bus (A0 - A15). The DSP can address three 64k x 24
memory spaces: P (Program), Dx (Data X), and Dy (Data Y). These
additional RAM spaces are decoded using PS* (Program Strobe), DS*
(Data Strobe), and X/Y*. RD* and WR* are separate read and write
strobes.
The ADSIC provides additional memory decoding logic for the RAMs
in the form of RSEL* used in decoding U403. RSEL* provides the logic
A13 x A14. U415 provides logic in the form of A13 + A14 for decoding
U414. RSEL* logic is programmed by the MCU through the SPI bus
interface.
The ADSIC also provides memory decoding for the FLASH ROM
(U404). EPS* provides the logic A15 x (A14 ≈ A13) and is use as a select
for the ROM. The ADSIC provide three bank lines for selecting 16k
byte banks from the ROM. This provides decoding for 128K bytes from
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