Motorola ASTRO Digital Saber Service Manual page 50

DIN and DIN* are the data lines in which the I and Q data words are
transferred from the ABACUS. These signals make up a deferentially
encoded current loop. Instead of sending TTL type voltage signals, the
data is transferred by flowing current one way or the other through the
loop. This helps reduce internally generated spurious emissions on the
transceiver board. The ADSIC contains an internal current loop
decoder which translates these signals back to TTL logic and stores the
data in internal registers.
In the fundamental mode of operation, the ADSIC transfers raw IF data
to the DSP. The DSP can perform IF filtering and discriminator
functions on this data to obtain a baseband demodulated signal.
However, the ADSIC contains a digital IF and discriminator function
and can provide this baseband demodulated signal directly to the DSP,
this being the typical mode of operation. The internal digital IF filter
is programmable up to 24 taps. These taps are programmed by the
MCU through the SPI interface.
The DSP accesses this data through its SSI serial port. This is a 6 port
synchronous serial bus. It is actually used by the DSP for both transmit
and receive data transferal, but only the receive functions will be
discussed here. The ADSIC transfers the data to the DSP on the SRD
line at a rate of 2.4MHz. This is clocked synchronously by the ADSIC
which provides a 2.4MHz clock on SC0. In addition, a 20kHz interrupt
is provided on SC1 signaling the arrival of a data packet. This means a
new I and Q sample data packet is available to the DSP at a 20kHz rate
which represents the sampling rate of the received data. The DSP then
processes this data to extract audio, signaling, etc. based on the 20kHz
interrupt.
In addition to the SPI programming bus, the ADSIC also contains a
parallel configuration bus consisting of D8-D23, A0-A2, A13-A15, RD*,
and WR*, This bus is used to access registers mapped into the DSP
memory starting at Y:FFF0. Some of these registers are used for
additional ADSIC configuration controlled directly by the DSP. Some
of the registers are data registers for the speaker D/A. Analog speaker
audio is processed through this parallel bus where the DSP outputs the
speaker audio digital data words to this speaker D/A and an analog
waveform is generated which is output on SDO (Speaker Data Out). In
conjunction with the speaker D/A, the ADSIC contains a
programmable attenuator to set the rough signal attenuation.
However, the fine levels and differences between signal types is
adjusted through the DSP software algorithms. The speaker D/A
attenuator setting is programmed by the MCU through the SPI bus.
The ADSIC provides an 8kHz interrupt to the DSP on IRQB for
processing the speaker data samples. IRQB is also one of the DSP mode
configuration pins at start up. This 8kHz signal must be enabled
through the SPI programming bus by the MCU and is necessary for
any audio processing to occur.
For secure messages, the analog signal data may be passed to the secure
module prior to processing speaker data for decryption. The DSP
transfers the data to and from the secure module through it's SCI port
consisting of TXD and RXD. The SCI port is a two wire duplex
asynchronous serial port. Configuration and mode control of the
secure module is performed by the MCU through the SPI bus.
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