Block Diagrams - JVC DR-M10SEF Service Manual

Block diagrams

DIGITAL 0 2
IEEE1394
controller
PHY_RESET[L]
IC1801
PHY_LREQ PHY_CLK
PHY_CNA PHY_CTL[0],[1]
PHY_DATA[0-7] PHY_LPS
PHY_LINK_ON
IEEE1394 section (SHEET 2)
SDRAM_DQ16 to 31
RA1609 to
SDRAM_DQ0 to 15
RA1612
SDRAM_A0 to 15
RA1625 to
SDRAM_CKE
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_WE_L
SDRAM_DQM0 to 3
SDRAM_DQS0 to 3
SDRAM_CLK0,1
SDRAM_CLK_L0,1
Media
processor
IC1401
IC1406
IC1407
RD/WR[L] ALE OE[L]/LDS[L] MADD1 to 22 CS[0] F_PROT[H] E5_RESET[L]
Media processor (SHEET 4)
2-4 (No.XA020SCH)
TPA+ TPA- TPB+ TPB-
RA1613 to DDR_DQ16 to 31
RA1616
DDR SDRAM DDR SDRAM
DDR_DQ0 to 15
IC1601 IC1602
DDR_BA1,2
DDR_A0 to 12
RA1628
DDR_CKE
DDR_RAS_L
DDR_CAS_L
R1601 to
DDR_WE_L
R1604
DDR_DQM0 to 3
R1653 to
DDR_DQS0 to 3
R1660
DDR_CLK0,1
R1613 to DDR_CLK_L0,1
R1616
DDR SDRAM section (SHEET 3)
ATA_DMAACK[L] ATA_INTRQ ATA_ADD1 to 4
ATA_DIOR[L] ATA_DIOW[L] ATA_IORDY
ATA_DAT0 to 15 ATA_RESET ATA_DMARQ
SYS_RESET[L] VIDEO_RXD
K_BUS_CLK K_BUS_REQ K_BUS_IN/OUT
VIDEO_RST[L] SPI_MOSI SPI_CLK VIDEO_CS
J4112
IEEE1394
terminal
TO CN4101
SHEET 10
TO CN4102
SHEET 10
ATA_DATA0 to 15
P_CTL[H] ATA_RESET
ATA_DMARQ
ATA_IORDY ATA_INTRQ
ATA_DMAACK[L] ATA_ADD0 to 4
ATA_DIOW[L] ATA_DIOR[L]
CIN VYIN SYNCDET CROUT CBOUT
YVOUT COUT RYOUT RCOUT
AO_FSYNC AO_D[0] DAC_RST[L]
AO_SCLK A_DAC_CS AO_MCLKO
DAC_CVBS_OUT
DAC_SCL DAC_Y_OUT DAC_SDA
DAC_SY_OUT
480I[H]
DAC_SC_OUT
VI_D2 to 9 VIDEO_RST[L] VO_D1 to 15 SPI_MOSI
VIDEO_27M VIDEO_CS VIDEO_MUTE[M] SPI_CLK VIDEO_RXD
SYS_RESET[L] K_BUS_CLK K_BUS_REQ K_BUS_IN K_BUS_OUT
AO_IEC958 AI_D[0] A_MUTE2[H] DAC_RST[L]
Video signal control section (SHEET 5)
RSTATA
20bit FET
HD_AT0 to 15 ATA_A0 to 2
Bas switch
IC2201
DMARQ IORDY CS1FX CS3FX
FET Bas switch DIOW DIOR DMACK INT_ATA
IC2202
ATAPI Interface section (SHEET 6)
MADD1 to 22
65Mbit Flash
RD/WR[L] E5_RESET[L] OE[L]/LDS[L] CS[0]
ALE MADD6 to 21
FLASH-ROM section(SHEET 7)
Video
controller
IC1001
AP A0 to A9
UDQM WE
CAS RAS
DQ0 to DQ15
16M SDRAM
IC1002
TO
DVD
Recorder unit
IC1201
LH_AR6 to 21
IC1202
IC1203