Media Processor Section - JVC DR-M10SEF Service Manual

Media processor section

AO_D[0]
AO_SCLK
AO_FSYNC
TO SHEET 5
AO_IEC958
AO_MCLKO
AI_D[0]
VIDEO_MUTE[H]
TO SHEET 2
PHY_CNA
480I[H]
TO SHEET 5
R1408 1k
D3.3V
R1409 10k
R1410 10k
TL1407
R1411 100
R1412 10k
R1413 10k
VI_D[2]
VI_D[3]
VI_D[4]
VI_D[5]
VI_D[6]
VI_D[7]
VI_D[8]
VI_D[9]
R1414
R1415
V3.3V
R1416
K1407 R1417
SHORT
R1402
TL1489
0Ω
C1450
0. 1
X1401
NAX0580-001X
VO_D[0]
VO_D[1]
VO_D[2]
VO_D[3]
VO_D[4]
VO_D[5]
VO_D[6]
VO_D[7]
VO_D[8]
VO_D[9]
VO_D[10]
VO_D[11]
VO_D[12]
VO_D[13]
VIDEO_27M
VI_D[2-9] VO_D[14]
VI_D[2-9]
VO_D[0-15] VO_D[15]
VO_D[0-15]
R1419
TL1412
TL1490
TL1491
TO SHEET 5
R1420
R1421 OPEN R1485
DAC_CVBS_OUT
R1422 OPEN R1486
DAC_SY_OUT
R1423 OPEN R1487
DAC_SC_OUT
R1424 OPEN R1488
DAC_Y_OUT
R1425 OPEN R1489
DAC_PB_OUT
R1426 OPEN R1490
DAC_PR_OUT
VDDI1.8 0. 1
C1452
V3.3V
R1493
0Ω C1453
K1408 0. 1
SHORT OPEN
D1401
C1454
C1455 0. 1
C1456 OPEN
TL1413
TL1414
TL1415
R1491 1k
TL1417
TL1418
TL1419
R1427 100 TL1420
PHY_DATA[7]
PHY_DATA[6]
PHY_DATA[5]
PHY_DATA[4]
PHY_DATA[3]
PHY_DATA[2]
PHY_DATA[1]
PHY_DATA[0-7] PHY_DATA[0]
PHY_DATA[0-7]
R1428
PHY_CTL[1]
R1429
PHY_CTL[0]
TO SHEET 2
R1430
PHY_LREQ
R1431
PHY_LPS
PHY_LINK_ON
PHY_CLK
DIGI3.3V
D2.5V
TO SHEET 5 B1401
D1.8V
LC1401
GND OPEN NQR0415-002X
C1403
0. 1
C1401 C1402 C1404 C1405 C1406
0. 1 0. 1 100 0. 1 0. 1
/6.3
B1402 LC1402
OPEN NQR0415-002X
C1408 C1409 C1440 C1441 C1411 C1412
0. 1 0. 1 0. 1 0. 1 100 0. 1
/6.3
B1403 LC1403
D5.0V
OPEN NQR0415-002X
C1417
TO SHEET 5 D1.8V
0. 1
D2.5V C1418
0. 1
GND
C1413 C1414 C1415 C1416
100 0. 1 OPEN 0. 1
C1433 C1432 C1431 C1426 /6.3
C1449 C1443 C1407 C1410
0. 1 0. 1 0. 1 0. 1
0. 1 0. 1 0. 1 0. 1
D3.3V
SSTL2_VDD
TO SHEET 3
VDDI1.8
GND
2-10 (No.XA020SCH)
CLKI
TL1402
CLKX
TL1437
CLKO_DAC/GPIOExt[35]
BYPASS_PLL
TL1403
EPD[L]
TL1404
RSTO[L]
TCK
TDI
TDO
TMS
TRST[L]
VI_D[0]
VI_D[1]
VI_D[2]
VI_D[3]
VI_D[4]
VI_D[5]
VI_D[6]
VI_D[7]
VI_D[8]
VI_D[9]
1k
VI_E[0]
1k
VI_VSYNC[0]
VI_CLK[0]
1k
VI_CLK[1]
1k
VI_VSYNC[1]/IvGPIOExt[45]
VI_E[1]/IvGPIOExt[29]
VO2_D[0]
VO2_D[1]
VO2_D[2]
VO2_D[3]
VO2_D[4]
VO2_D[5]
VO2_D[6]
VO2_D[7]
VO2_D[8]
VO2_D[9]
VO_D[0]/IvGPIOExt[0]
VO_D[1]/IvGPIOExt[1]
RA1401
VO_D[2]/IvGPIOExt[2]
100
VO_D[3]/IvGPIOExt[3]
VO_D[4]/IvGPIOExt[4]
VO_D[5]/IvGPIOExt[5]
RA1402
VO_D[6]/IvGPIOExt[6]
100
VO_D[7]/IvGPIOExt[7]
VO_D[8]/IvGPIOExt[8]
VO_D[9]/IvGPIOExt[9]
RA1403
VO_D[10]/IvGPIOExt[10]
100
VO_D[11]/IvGPIOExt[11]
VO_D[12]/IvGPIOExt[12]
VO_D[13]/IvGPIOExt[13]
RA1404
VO_D[14]/IvGPIOExt[14]
100
VO_D[15]/IvGPIOExt[15]
100
VO_E/IvGPIOExt[30]
VO_ACTIVE
VO_HSYNC
VO_VSYNC
100
VO_CLK
OPEN
DAC1_OUT
OPEN
DAC2_OUT
OPEN
DAC3_OUT
OPEN
DAC4_OUT
OPEN
DAC5_OUT
OPEN
DAC6_OUT
DAC_DVSS_1
DAC_DVDD
DAC_VDD_0
DAC_VDD_3
D1402
DAC4_OUTB
DAC2_OUTB
USB_AVDD_0
USB_AVDD_1
USB_AGND_0
USB_AGND_1
DPLUS_0
DMINUS_0
HOST_PO_0
HOST_OC_0
DPLUS_1
DMINUS_1
HOST_PO_1/GPIOExt[43]
HOST_OC_1/GPIOExt[44]
USB_48MHz/GPIOExt[36]
1394_PHY_DATA[7]
1394_PHY_DATA[6]
RA1405
1394_PHY_DATA[5]
100
1394_PHY_DATA[4]
1394_PHY_DATA[3]
1394_PHY_DATA[2]
RA1406
1394_PHY_DATA[1]
100
1394_PHY_DATA[0]
100
1394_PHY_CTL[1]
100
1394_PHY_CTL[0]
100
1394_LREQ
100
1394_LPS
1394_LINK_ON
1394_PHY_CLK
K1402
SHORT
T T
C1442
0. 1
SSTL2_VDD C1419 C1420 C1421 C1422 C1423 C1424 C1425 K1403
OPEN 10 0. 1 0. 1 0. 1 0. 1 0. 1 SHORT
/6.3
C1444
# K1404 0. 1
T
C1427 C1428 C1429 C1430
10 0. 1 0. 1 0. 1
/6.3
K1401
SHORT K1405 # K1406
OPEN
T T
C1434 C1435 C1436 C1437 C1438 C1439 C1445 C1446
OPEN 10 0. 1 0. 1 0. 1 0. 1 0. 1 0. 1
/6.3
IC1401
D5.0V
TO SHEET 5
R1471 100
ALE
R1470 1k R1472 0'
RST[L]
R1469 1k C1459 OPEN
MCONFIG
CS0_8BIT
R1468 100
LDS[L]/OE[L]
R1467 100
UDS[L]/UWE[L]
R1466 100
GPIO[0]
R1465 100
GPIO[1]
TL1486
GPIO[2]
TL1485
GPIO[3]
R1462 100
GPIO[4]/PCMCIA_IOW[L]
R1461 100
GPIO[5]/PCMCIA_IOR[L]
R1460 100
WR[L]/LWE[L]
R1459 100
WAIT[L]
R1458 100
DTACK[L]
CS[5]
CS[4]
CS[3]
CS[2]
R1453 100 CS[1]
CS[1]
R1452 100 CS[0]
CS[0]
MADDR[26]
MADDR[25]
MADDR[24]
MADDR[23]
R1451 100 MADD[22]
MADDR[22]
R1450 100 MADD[5]
MADDR[5]
MADD[4]
MADDR[4]
RA1411 MADD[3]
MADDR[3]
100 MADD[2]
MADDR[2]
MADD[1]
MADDR[1]
MADD[21]
MADDR[21]/MDATA[15]
RA1410 MADD[20]
MADDR[20]/MDATA[14]
100 MADD[19]
MADDR[19]/MDATA[13]
MADD[18]
MADDR[18]/MDATA[12]
MADD[17]
MADDR[17]/MDATA[11]
RA1409 MADD[16]
MADDR[16]/MDATA[10]
100 MADD[15]
MADDR[15]/MDATA[9]
MADD[14]
MADDR[14]/MDATA[8]
MADD[13]
MADDR[13]/MDATA[7]
RA1408 MADD[12]
MADDR[12]/MDATA[6]
100 MADD[11]
MADDR[11]/MDATA[5]
MADD[10]
MADDR[10]/MDATA[4]
MADD[9]
MADDR[9]/MDATA[3]
RA1407 MADD[8]
MADDR[8]/MDATA[2]
100 MADD[7]
MADDR[7]/MDATA[1]
MADD[6]
MADDR[6]/MDATA[0]
ATA_ADD[0]
ATAPI_ADDR[0]
ATA_ADD[1]
ATAPI_ADDR[1]
ATA_ADD[2]
ATAPI_ADDR[2]
ATA_ADD[3]
ATAPI_ADDR[3]
ATA_ADD[4]
ATAPI_ADDR[4]
ATA_DAT[15]
ATAPI_DATA[15]
ATA_DAT[14]
ATAPI_DATA[14]
ATA_DAT[13]
ATAPI_DATA[13]
ATA_DAT[12]
ATAPI_DATA[12]
ATA_DAT[11]
ATAPI_DATA[11]
ATA_DAT[10]
ATAPI_DATA[10]
ATA_DAT[9]
ATAPI_DATA[9]
ATA_DAT[8]
ATAPI_DATA[8]
ATA_DAT[7]
ATAPI_DATA[7]
ATA_DAT[6]
ATAPI_DATA[6]
ATA_DAT[5]
ATAPI_DATA[5]
ATA_DAT[4]
ATAPI_DATA[4]
ATA_DAT[3]
ATAPI_DATA[3]
ATA_DAT[2]
ATAPI_DATA[2]
ATA_DAT[1]
ATAPI_DATA[1]
ATA_DAT[0]
ATAPI_DATA[0]
ATAPI_RESET
ATAPI_DMAACK[L]
ATAPI_DMARQ
ATAPI_IORDY
ATAPI_INTRQ
ATAPI_DIOR[L]
ATAPI_DIOW[L]
ATAPI2_RESET
ATAPI2_DMAACK[L]
R1498 10k
ATAPI2_DMARQ
R1497 10k
ATAPI2_IORDY
R1496 10k
ATAPI2_INTRQ
ATAPI2_DIOR[L]
ATAPI2_DIOW[L]
ATAPI2_ADDR[0]
ATAPI2_ADDR[1]
ATAPI2_ADDR[2]
ATAPI2_ADDR[3]
ATAPI2_ADDR[4]
TL1464
ATAPI2_DATA[15]
TL1463
ATAPI2_DATA[14]
TL1462
ATAPI2_DATA[13]
TL1461
ATAPI2_DATA[12]
TL1460
ATAPI2_DATA[11]
TL1459
ATAPI2_DATA[10]
TL1458
ATAPI2_DATA[9]
TL1457
ATAPI2_DATA[8]
ATAPI2_DATA[7] TL1456
TL1455
ATAPI2_DATA[6]
ATAPI2_DATA[5] TL1454
TL1453
ATAPI2_DATA[4]
ATAPI2_DATA[3] TL1452
TL1451
ATAPI2_DATA[2]
ATAPI2_DATA[1] TL1450
TL1449
ATAPI2_DATA[0]
D1403
1SS355
R1441
10k
C1457 C1458
0. 1 0. 1
TO SHEET 5
SDRAM_A[14-17]
SDRAM_A[14-17]
SDRAM_VREF
SDRAM_CLK_L[1]
SDRAM_CLK_L[1]
SDRAM_CLK[1]
SDRAM_CLK[1]
SDRAM_CLK_L[0]
SDRAM_CLK_L[0]
SDRAM_CLK[0]
SDRAM_CLK[0]
SDRAM_WE_L
SDRAM_WE_L
SDRAM_CKE TO SHEET 3
SDRAM_CKE
SDRAM_RAS_L
SDRAM_RAS_E
SDRAM_CAS_L
SDRAM_CAS_L
SDRAM_DQM[0-3]
SDRAM_DQM[0-3]
SDRAM_DQS[0-3]
SDRAM_DQS[0-3]
SDRAM_A[0-12]
SDRAM_A[0-12]
SDRAM_DQ[16-31]
SDRAM_DQ[16-31]
SDRAM_DQ[0-15]
SDRAM_DQ[0-15]
AL E
OE[L]/LDS[L]
UWE[L]/UDS[L]
ELINK_INT[L]
RD/WR[L]
WAIT[L]
TO SHEET 7
DTACK[L]
CS[1]
CS[0]
MADD[22]
MADD[1-5]
MADD[1-5]
MADD[6-21]
MADD[6-21]
/MDT[0-15]
TO SHEET 2
PHY_RESET[L]
TO SHEET 5
DAC_RST[L]
ATA_ADD[0-4]
ATA_ADD[0-4]
ATA_DAT[0-15]
ATA_DAT[0-15]
ATA_RESET
ATA_DMAACK[L]
TO SHEET 6
ATA_DMARQ
ATA_IORDY
ATA_INTRQ
ATA_DIOR[L]
ATA_DIOW[L]
R1445 100
K_BUS_CLK
R1446 100
K_BUS_REQ
TO SHEET 5
R1447 100
SYS_RESET[L]
R1448 100
K_BUS_OUT
R1449 100
K_BUS_IN
E5_RESET[L]
TO SHEET 7
UART2_TX
UART2_RX
SHEET 4