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Related Manuals for Midas RTE-V831-PC
Summary of Contents for Midas RTE-V831-PC
- Page 1 RTE-V831-PC USER ’S MANUAL (Rev. 2.00) RTE-V831-PC USER ’S MANUAL (Rev. 2.00) Midas lab...
- Page 2 RTE-V831-PC USER ’S MANUAL (Rev. 2.00) REVISION HISTORY Date REV. Chapter Explanation of revision Apr. 14 1997 1.02 First edition Apr. 28 1998 2.00 A description of the use of the PARTNER monitor has been added. Corrections have been made to the following descriptions: JCPU-A, pin 26 (+3..3 V →...
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Page 3: Table Of Contents
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) CONTENTS INTRODUCTION ........................1 1.1. NUMERIC NOTATIO N ........................1 FUNCTIONS..........................1 MAJOR FEATURES........................ 2 BASIC SPECIFICATIONS....................... 2 BOARD CONFIGURATION..................... 3 5.1. RESET SWITCH (R ESET) .........................3 5.2. POWER JACK (JPOWER) .........................3 5.3. SWITCH 1 (SW1) ..........................3 5.4. - Page 4 RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 10. EXT BUS SPECIFICATIONS....................24 10.1. PIN ARRANGEMENT AND SIGNALS..................24 10.2. TIMING..............................25 10.3. NOTES ON USING THE EXT BUS....................26 11. SOFTWARE .......................... 27 11.1. INITIALIZATION..........................27 11.2. LIBRARIES ............................27 11.3. USING TIMERS ..........................28 11.4.
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Page 5: Introduction
The GHS Multi or NEC PARTNER source-level debugger can be used as a development software tool with the RTE-V831-PC. The type of monitor to be stored in ROM depends on the debugger type. In ROM, the monitor specified at the time of purchase is stored. Even when neither of the debuggers is purchased together with the RTE-V831-PC, they can be purchased at anytime subsequently. -
Page 6: Major Features
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) MAJOR FEATURES • Two types of monitor ROM are provided: one is used for the Green Hills Multi and the other for the NEC PARTNER. • Real-time execution and evaluation at a high-level language level using Multi or PARTNER. -
Page 7: Board Configuration
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) BOARD CONFIGURATION The physical layout of the major components on the RTE-V831-PC board is shown below. This chapter explains each component. S I M M # 2 5 V - > 3 V J S I O 2... -
Page 8: Switch 2 (Sw2)
The LEDs are used to indicate statuses, as listed below. Description POWER Lights when power is supplied to the RTE-V831-PC board. Lights in green when voice is output. Lights in red if an error occurs during voice output. Lights in green when voice is recorded. -
Page 9: Clock Socket (Osc1)
SIMMs (for DOS/V). Never mount a SIMM of more than 8M bytes. 5.9. ROM SOCKETS The RTE-V831-PC has ROM sockets to hold 40-pin ROM chips to provide standard 128K bytes × (64K 16 bits). When the ROM chips used here are to be replaced, their type should be 27C1024, 27C2048, or 27C4096, and the access time should be 150 ns or less. -
Page 10: Jp3, Jp4, Jp5
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 5.12. JP3, JP4, JP5 Use jumpers JP3, JP4, and JP5 as set at the factory. JP3: Open JP4: Closed JP5: Closed 5.13. JUMPER FOR SWITCHING BETWEEN BASIC CLOCKS FOR USER TIMERS (JP6) JP6 is used to select which of two clocks is to be supplied to the timers (CH#1, CH#2) that can be used by applications. -
Page 11: Parallel Connector (Jprt)
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 5.15. PARALLEL CONNECTOR (JPRT) The JPRT connector is used for parallel communication controlled by the parallel (printer) controller (TL16C552A). JPRT is a pin plug type connector with a 2.54 mm pitch. All signals on the connector are 5-V level signals. -
Page 12: Debugging Connector (Jdbg)
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 5.17. DEBUGGING CONNECTOR (JDBG) The JDBG connector is used to connect a debug tool based on the debug function built into the V831. On-board connector: 8930E-040-178MS manufactured by KEL Pin No. Signal name Pin No. -
Page 13: Cpu Connector (Jcpu-A, Jcpu-B)
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 5.19. CPU CONNECTOR (JCPU-A, JCPU-B) The CPU connector signals are connected directly to the V831. Many signals are used on the board. So, be careful when extracting signals from the JCPU. The 3.3-V signal level is used. - Page 14 RTE-V831-PC USER ’S MANUAL (Rev. 2.00) Pin No. Signal name Pin No. Signal name INTP01 INP00 TCLR INTP13 INTP11 INTP12/TO11 INTP10/TO10 CS7- CS6- CS5- CS4- CS3- CS2- CS1- HLDAK- HLDRQ- READY- BCYST- IORD- IOWR- TRCDATA3 TRCDATA2 TRCDATA1 TRCDATA0 CLKOUT RAS-...
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Page 15: Connection With The Host Pc
INSTALLATION ON THE ISA BUS When the RTE-V831-PC is installed in the ISA bus slot of the PC, power (+5 V) is supplied from the ISA bus to the board. In addition, the ISA bus can be used for communication with the debugger, so programs are down-loaded at high speed. -
Page 16: Hardware References
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) HARDWARE REFERENCES This chapter describes the hardware of the RTE-V831-PC. 7.1. MEMORY AND I/O MAP The figure below shows the memory and I/O mapping on the board. 0 0 0 0 - 0 0 0 0... -
Page 17: Details Of Mapping
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 7.2. DETAILS OF MAPPING Detailed information on mapping is provided below. CS0 space (x000-000 to x0FF-FFFF, x800-000 to x8FF-FFFF) CS0 is the space for EDO-DRAM mounted in the SIMM#1 and SIMM#2 sockets. The size of the CS0 space is 16M bytes while it has a data bus width of 32 bits. -
Page 18: System-I/O
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) SYSTEM-I/O SYSTEM-I/O represents I/O devices mapped into the CS5 space. The I/O devices include the Audio, UART/PRINTER, TIC, PIO, and ISA bus interface. This chapter explains these devices. (A description of the ISA bus interface is omitted.) 8.1. -
Page 19: 7-Segment Led Display Data Output Port (4500-2000H [Write Only])
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 8.3. 7-SEGMENT LED DISPLAY DATA OUTPUT PORT (4500-2000H [WRITE ONLY]) This port sets the data to be displayed on the 7-segment LED. The table below indicates the data format. When a bit is set to 0, the corresponding segment is turned on. -
Page 20: Command Register #2 Port (4500-5000H [Read/Write])
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 8.6. COMMAND REGISTER #2 PORT (4500-5000H [READ/WRITE]) This port has the following functions: Data bus Logical address Register 4500-5000H FRES TOVEN C M D # 2 (initial value) TOVEN: Controls the use of the time-over function. When the length of a bus cycle reaches 512 bus clocks, the time-over function returns READY-, and forcibly terminates the bus cycle. -
Page 21: Tic ( M Pd71054) (4500-B000H To 4500-B00Ch)
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 8.8. TIC ( PD71054) (4500-B000H TO 4500-B00CH) The NEC PD71054 is installed as a TIC. The PD71054 is compatible with the Intel i8254. It has three timers/counters. These timers/counters are used to generate monitor timer interrupts. -
Page 22: Interrupt Controller (Pic) (4500-D000H To 4500-D018H)
The PIC mainly exercises interrupt-related control. The table below indicates the assignment of registers. With the RTE-V831-PC, INT0 of the PIC is connected to NMI or INTP03 of the V831 according to the specification of NMI/INT3-. INT1 is connected to INTP02. Data bus... -
Page 23: Audio Controller (Audcnt) (4580-0000H To 4580-0010H, 4580-2000H)
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 8.10. AUDIO CONTROLLER (AUDCNT) (4580-0000H TO 4580-0010H, 4580-2000H) AUDCNT controls digital data input to and output from the audio chip ( PD63310). Logical address Register Data bus 4580-0000H C O N T R O L... - Page 24 RTE-V831-PC USER ’S MANUAL (Rev. 2.00) The STATUS register is a read-only register for indicating various statuses. Replay status Stopped Being conducted Overflow upon replay No overflow detected Overflow detected Underflow upon replay No underflow detected Underflow detected FIFO for replay...
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Page 25: Pd63310 Register: Audio Cod. (4580-1000H To 4580-100Fh)
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) The MCLKDIV register is used to determine the MCLK frequency. MCLK Sampling frequency Bytes/sec DIV4 DIV3 DIV2 DIV1 DIV0 49.152/(DIV + 2) (MCLK/256) fs * 4 24.576 MHz 16.384 MHz 12.288 MHz 48.0 KHz 192.0 KB... -
Page 26: Interrupts And Dma
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) INTERRUPTS AND DMA This chapter describes the interrupts and DMA for the RTE-V831-PC. 9.1. INTERRUPT External interrupts are used as indicated below. Interrupt Source Interrupt from the ROM emulator, and INT0 interrupt by PIC setting (for the monitor) -
Page 27: Dma Channel
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 9.3. DMA CHANNEL DMARQ-/AK- DMARQ signal Remark Replay request A DMA request for data to be written to the audio data buffer during replay. A timeout results in an underrun error. Recording request A DMA request for data to be read from the audio data buffer during recording. -
Page 28: Ext Bus Specifications
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 10. EXT BUS SPECIFICATIONS The EXT bus, provided with JEXT connectors, is used to expand the memory and I/O units. The local bus of this board is connected to the JEXT connector. 10.1. PIN ARRANGEMENT AND SIGNALS The following table shows the pin arrangement of the JEXT connector. -
Page 29: Timing
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) JEXT Pin Arrangement 10.2. TIMING The timing of the EXT bus is shown below. A[0..19] A[0..19] B H E - B H E - T 1 0 T 1 1 High R D -... -
Page 30: Notes On Using The Ext Bus
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 10.3. NOTES ON USING THE EXT BUS When extending hardware on the EXT bus, note the following points. Memory and I/O space mapping The EXT bus space is mapped onto the CS4 space of the V831. For access, select memory or I/O space with the bus controller (BCTC) built into the CPU. -
Page 31: Software
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 11. SOFTWARE This chapter describes the initialization of the hardware of the RTE-V831-PC board, and explains how to use peripheral devices. 11.1. INITIALIZATION The boot routine initializes the bus controller built into the V831 for external memory or I/O access. The wait control and DRAM timing values indicated below assume a bus clock of 33 MHz. -
Page 32: Using Timers
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 11.3. USING TIMERS A sample time measurement is indicated below which uses timer 1 and timer 2 cascaded with each other by an external timer (8254) on the board. Timer 1 is initialized as an interval counter (mode 2), and timer 2 is initialized as a down counter (mode 0). -
Page 33: Flash Rom Programming
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 11.4. FLASH ROM PROGRAMMING A sample program for writing data into a flash ROM mounted on the board is indicated below. For writing to a flash ROM, data is written on a byte-by-byte basis in the uncacheable area. For detailed information about the programming algorithm, refer to the data sheet for the flash ROM. - Page 34 RTE-V831-PC USER ’S MANUAL (Rev. 2.00) /* Confirm EPROM boot * / i f ( i n b ( 0 x 4 5 0 0 1 0 0 0 ) & 0 x 8 0 ) = = 0 ) { r e t u r n - 1 ;...
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Page 35: Audio I/O
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 11.5 AUDIO I/O A sample program using the audio input/output interface mounted on the board is indicated below. For data input/output, the DMA built into the V831 is used. /* Audio input/output sample */... - Page 36 RTE-V831-PC USER ’S MANUAL (Rev. 2.00) return 0; /* Use record processing DMA1 * / A u d i o R e c o r d ( i n t a d d r , i n t s i z e )
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Page 37: Development Of Applications Using Maskable Interrupts
However, a program running on the monitor must rewrite the alternate vector area to enable an interrupt. With the monitor of the RTE-V831-PC, an alternate vector area is allocated at FE07-0000H to FE07- 01FFH in SRAM. So, for an interrupt with exception code FE00H, an instruction for causing a branch to the interrupt handling routine is to be written at address FE07-0000H;... -
Page 38: Internal Instruction Ram
HCCW system register). When this function is used, the vector setting requirement does not differ between an ordinary V831 program and a program using the monitor on the RTE-V831-PC. For an explanation of the method of vector usage with the internal instruction RAM and that of modifying the contents of the internal instruction RAM, refer to the manual provided with the CPU. -
Page 39: Restrictions On Breaks In The Interrupt Handling Routine
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 12.4. RESTRICTIONS ON BREAKS IN THE INTERRUPT HANDLING ROUTINE The following restrictions are imposed on breaks in the interrupt handling routine: 1) During a break, all maskable interrupts are rejected. 2) The single step function sets a temporary breakpoint in the next instruction. So, when a user program placed in the EI (interrupt enable) state is subject to single stepping, an interrupt is accepted even during single stepping. -
Page 40: Appendix A Multi Monitor
PC. Refer to the RTE for Win32 Installation Manual (supplied with this product) for installation and test methods. 13.2. SWITCH SETTING The RTE-V831-PC board has two DIP switches. The DIP switches can be used to set up the evaluation board. The switch layout is shown below. 5V -> 3V... -
Page 41: Sw2 Setting
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) Debug mode Setting 7-segment LED used by the monitor Normal use state (Factory-set) Debug Mode Setting Break interrupt Setting INTP3 used (Factory-set) NMI used Break Interrupt Setting SW1-7 is not used with the Multi monitor. -
Page 42: Multi Monitor
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 13.3. MULTI MONITOR The ROM chip on the board is incorporated with the Multi monitor. The following cautions should be observed when the board is connected to the Multi debugger as the host. 13.3.1. Monitor Work RAM The monitor uses the first 64K bytes area in the SRAM as work RAM. -
Page 43: Rte Commands
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 13.4. RTE COMMANDS When the monitor and server are connected, the TARGET window is opened. The RTE commands can be issued in this window. The following table lists the RTE commands. Command Description HELP, ? Displays help messages. -
Page 44: Outb, Outh, Outw
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 13.4.5. OUTB, OUTH, OUTW <Format> OUTB [[address] data] OUTH [[address] data] OUTW [[address] data] Writes to an I/O register. The OUTB, OUTH, and OUTW commands access in byte, halfword, and word units, respectively. If an address or data is omitted, the previous address or data is assumed. -
Page 45: Appendix B Partner Monitor
PARTNER monitor stored in ROM and the debugger on the host. It also provides notes on the use of the PARTNER monitor. 14.1. SWITCH SETTING The RTE-V831-PC board has two DIP switches. The DIP switches can be used to set up the evaluation board. The switch layout is shown below. 5V -> 3V... -
Page 46: Sw2 Setting
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) Break interrupt Setting INTP3 used (Factory-set) NMI used Break Interrupt Setting SW1-7 is not used with the monitor. Boot-time bus size (BT16B) and ROM Setting Boot on 32-bit bus (BT16B = 0) from flash ROM... -
Page 47: Partner Monitor
RTE-V831-PC USER ’S MANUAL (Rev. 2.00) 14.2. PARTNER MONITOR 14.2.1. Monitor Work RAM The monitor uses the first 64K bytes area in the SRAM as work RAM. In other words, user programs are not allowed to use logical addresses FE07-0000H to FE07-FFFFH. - Page 48 RTE-V831-PC USER ’S MANUAL (Rev. 2.00) - Memo - RTE-V831-PC User ’s Manual M6A1MNL01 Midas lab...
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