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Summary of Contents for Midas RTE-V821-PC
- Page 1 RTE-V821-PC User's Manual Midas lab...
- Page 2 RTE-V821-PC USER’ S MANUAL REVISION HISTORY Date of Revision Page Description enforcement August 11, 1995 First issue December 25, 1995 11, 12 Correction of error related to descriptions about SW2 (1-2 and 3-4) settings...
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Page 3: Table Of Contents
RTE-V821-PC USER’ S MANUAL CONTENTS INTRODUCTION.......................... 4 1.1. NUMERIC NOTATION......................4 FEATURES AND FUNCTIONS ..................... 5 BOARD CONFIGURATION ......................6 3.1. RESET SWITCH (SWRESET)....................6 3.2. POWER SUPPLY CONNECTOR (JPOWER)................. 6 3.3. SWITCH1 (SW1) ........................6 3.4. SWITCH2 (SW2) ........................7 3.5. - Page 4 RTE-V821-PC USER’ S MANUAL 8.1. RESET-..........................21 8.2. NMI-............................ 21 Multi MONITOR ......................... 22 9.1. MONITOR WORK RAM ...................... 22 9.2. INTERRUPTS ........................22 9.3. _INIT_SP SETTING ......................22 9.4. REMOTE CONNECTION ....................22 RTE COMMANDS ........................23 10.1. HELP (?) ..........................23 10.2.
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Page 5: Introduction
This manual describes the RTE-V821-PC, which is an evaluation board for the V821, NEC's CPU. With the RTE-V821-PC, it is possible to develop and debug programs, and evaluate the CPU performance, using the GreenHills Multi debugger. Communication with this debugger is carried out using the IBM-PC/AT ISA bus or RS-232C serial interface. -
Page 6: Features And Functions
RTE-V821-PC USER’ S MANUAL 2. FEATURES AND FUNCTIONS The overview of each function block of the RTE-V821-PC is shown below. JSUBPORT CONNECTOR USER V821 JEXT D-RAM S-RAM CONNECTOR Local Bus Internal ISA BUS I/F TIMER/SIO Control RS-232C ISA Bus CONNECTOR... -
Page 7: Board Configuration
RTE-V821-PC USER’ S MANUAL 3. BOARD CONFIGURATION The physical layout of the major components on the RTE-V821-PC board is shown below. This chapter explains each component. JEXT JPOWER DRAM SIMM SWRESET OSC1 V821 SCC/ TIMER JCPU SRAM RTE-V821-PC Board Top View 3.1. -
Page 8: Switch2 (Sw2)
RTE-V821-PC USER’ S MANUAL 3.4. SWITCH2 (SW2) SW2 is a switch for general-purpose input ports. When a switch contact is open, it corresponds to 1. When it is closed, it corresponds to 0. See Section 6.1.2 for details. 3.5. The LEDs are used to indicate statuses, as listed below. -
Page 9: Serial Connector (Jsio)
RTE-V821-PC USER’ S MANUAL Number Signal Description 1,3,5,7,9, 11,13,15 SCLK-/P07 Connected directly to the CPU and pulled up with 47 kΩ. SI/P05 Connected directly to the CPU and pulled up with 47 kΩ. SO/P06 Connected directly to the CPU and pulled up with 47 kΩ. -
Page 10: Cpu Test Pins (Jcpu)
The V821 can use a PLL for system clock generation. The PLL mode is selected according to the state of the TCLR/P00 pin at a reset. The TCLR/P00 pin is pulled down with 47 kΩ in the RTE-V821-PC, so the PLL mode is usually selected. In this case, the frequency of the oscillator or crystal connected to the OSC1 socket is one-fifth the system clock frequency. -
Page 11: Dram-Simm Sockets
The capacity of installed SIMMs can be detected using a PIO port. (See Section 6.1.2.) 3.12. ROM SOCKETS The RTE-V821-PC has a ROM socket, which is used to hold 40-pin ROM chips to provide standard 128 Kbytes (64K x16 bits). When the system clock frequency is 25 MHz, use ROM... -
Page 12: Installation And Use
4. INSTALLATION AND USE The RTE-V821-PC board is designed to be installed in the ISA bus slot of a PC/AT or compatible (hereafter called the PC). However, it can also be used as a standalone, if it is powered from an external power supply. -
Page 13: Installation On The Isa Bus
INSTALLATION ON THE ISA BUS When the RTE-V821-PC is installed in the ISA bus slot of the PC, power (+5V) is supplied from the ISA bus to the board. In addition, the ISA bus can be used for communication with the debugger, so programs are down-loaded at high speed. -
Page 14: Hardware References
Memory Map DRAM space (0000-0000H to 00FF-FFFFH) This space is in a 72-pin SIMM chip mounted on the RTE-V821-PC board. A 4-Mbyte SIMM chip is used in a standard configuration. It can be replaced with an 8- Mbyte or 16-Mbyte SIMM chip for memory expansion. -
Page 15: I/O Map
The standard ROM chip that is factory-set contains the Multi monitor. 5.2. I/O MAP The I/O space in the V821-CPU is not used in the RTE-V821-PC. The I/O registers used for control purposes are allocated in the memory-mapped SYSTEM-I/O space. This section explains how to set the internal I/O registers. -
Page 16: Dram Control Unit (Dramc)
5.2.7. Serial Control Unit (SCU) The UART function is not used in the RTE-V821-PC. However, TxD is used as the UBE- pin, so the UART transmission function is unavailable. Only the reception function is open to the user, because RxD is not used in the RTE-V821-PC. -
Page 17: Interrupt Control Unit (Icu)
Use of Interrupts 5.2.9. Bus Arbitration Unit (BAU) The bus arbitration unit is not used in the RTE-V821-PC. The CPU pins related to the bus arbitration unit (HLDRQ- and HLDAK-) are not used in the RTE-V821-PC either. 5.2.10. Clock Generator (CG) Clock pulses are generated from an oscillator or crystal mounted on the OSC1 socket. -
Page 18: System-I/O
RTE-V821-PC USER’ S MANUAL 6. SYSTEM-I/O SYSTEM-I/O is an I/O device mapped in a memory space. The I/O devices include the UART/TIMER, PIO, and ISA bus interface. (No description about the ISA bus interface is included.) 6.1. UART/TIMER (SCC2691) The SCC2691 UART receiver/transmitter LSI chip produced by PHILIPS Signetics is used as the UART/TIMER. - Page 19 RTE-V821-PC USER’ S MANUAL Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PORT0 LED-P07 LED-P06 Reserved field 0 Output PORT1 SW2[8..1] Input Reserved PORT2 PD[2..1] TOVERF- DSR- DTR- NMIMASK TOVERCLR- field 1 Input Output PIO Bit Assignment Each port bit is described below.
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Page 20: Jext Bus Specification
RTE-V821-PC USER’ S MANUAL 7. JEXT BUS SPECIFICATION The JEXT connector is used to expand memory and I/O units. The local bus on this board is connected to this connector. The following tables list the pin arrangement of the JEXT connector and the functions of each signal. - Page 21 RTE-V821-PC USER’ S MANUAL A[0..19] A[0..19] BHE- BHE- High High D[0..15] Dout D[0..15] READY READY Write cycle Read cycle JEXT Bus Cycle Description MIN(ns) MAX(ns) Symbol RD address setup time RD address hold-up time RD cycle time RD cycle interval...
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Page 22: Other Cpu Resources
RTE-V821-PC USER’ S MANUAL 8. OTHER CPU RESOURCES 8.1. RESET- The factors listed below trigger a CPU reset. They also system-reset the board control circuit. • Power-on reset : Occurs when the power to the board is switched on. •... -
Page 23: Multi Monitor
RTE-V821-PC USER’ S MANUAL 9. Multi MONITOR The ROM chip on the board is incorporated with the Multi monitor. The following cautions should be observed when the board is connected to the Multi server as the host. 9.1. MONITOR WORK RAM The monitor uses the SRAM area between the start address and 2000H as work RAM. -
Page 24: Rte Commands
RTE-V821-PC USER’ S MANUAL RTE COMMANDS When the monitor and server are connected, the TARGET window is opened. The RTE commands can be issued in this window. The following table lists the RTE commands. Command Description HELP, ? Displays help messages. -
Page 25: Outb, Outh, And Outw
RTE-V821-PC USER’ S MANUAL 10.5. OUTB, OUTH, AND OUTW <Format> OUTB [[address] data] OUTH [[address] data] OUTW [[address] data] Write to an I/O register. The OUTB, OUTH, and OUTW commands access in byte, halfword, and word units, respectively. If an address or data is omitted, the previous address or data is assumed. -
Page 26: Appendix
RTE-V821-PC USER’ S MANUAL APPENDIX 11.1. CPU PINS The following table lists the state of each CPU pin. CPU pin Reference item X1,X2 Connected to the OSC1 socket to 3.10., 5.2.10. implement a clock. CLKOUT Used as CLKOUT. 5.2.10. It is impossible to specify to disable clock output. - Page 27 RTE-V821-PC USER’ S MANUAL - Memo - RTE-V821-PC User's Manual M471MNL02 First issue: Rev1.0 on August 11, 1995. Revision: Rev1.1 on December 25, 1995 Midas lab...
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