Midas RTE-V830-PC User Manual
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Midas RTE-V830-PC User Manual

Midas RTE-V830-PC User Manual

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RTE-V830-PC
User's Manual
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  • Page 1 RTE-V830-PC User's Manual Midas lab...
  • Page 2 RTE-V830-PC USER’ S MANUAL REVISION HISTORY Date of enforcement Revision Page Description November 28, 1995 Preliminary issue December 25, 1995 0.91 6, 7,... Correction of error in which SW1 was written as SW2 and vice versa 9, 10 Correction of error related to descriptions about SW1...

  • Page 3: Table Of Contents

    RTE-V830-PC USER’ S MANUAL CONTENTS INTRODUCTION .......................4 1.1. NUMERIC NOTATION ....................4 FEATURES AND FUNCTIONS..................5 BOARD CONFIGURATION ....................6 3.1. RESET SWITCH (SWRESET) ..................6 3.2. POWER SUPPLY CONNECTOR (JPOWER) ............6 3.3. SWITCH 1 (SW1)......................6 3.4. SWITCH 2 (SW2)......................7 3.5. LED...........................7 3.6. TEST PINS (TP)......................7 3.7.
  • Page 4 RTE-V830-PC USER’ S MANUAL 9.3. _INIT_SP SETTING ....................24 9.4. REMOTE CONNECTION ..................24 10. RTE COMMANDS ......................25 10.1. HELP (?) .........................25 10.2. INIT .........................25 10.3. VER ........................25 10.4. INB, INH, AND INW ....................25 10.5. OUTB, OUTH, AND OUTW..................26 10.6. DCTR COMMAND....................26 10.7.

  • Page 5: Introduction

    This manual describes the RTE-V830-PC, which is an evaluation board for the V830, NEC's CPU. With the RTE-V830-PC, it is possible to develop and debug programs, and evaluate the CPU performance, using the GreenHills Multi debugger. Communication with this debugger is carried out using the IBM-PC/AT ISA bus or RS-232C serial interface.

  • Page 6: Features And Functions

    RTE-V830-PC USER’ S MANUAL 2. FEATURES AND FUNCTIONS The overview of each function block of the RTE-V830-PC is shown below. USER V830 JEXT D-RAM S-RAM CONNECTOR Local Bus Internal ISA BUS I/F TIMER/SIO Control RS-232C ISA Bus CONNECTOR RTE-V830-PC Block Diagram Features •...

  • Page 7: Board Configuration

    RTE-V830-PC USER’ S MANUAL 3. BOARD CONFIGURATION The physical layout of the major components on the RTE-V830-PC board is shown below. This chapter explains each component. JEXT JPOWER SIM-72pin X 2 (D0-15) (D16-31) SW RESET J1(1-36) J1(37-72) J1(109-144) POWER V830...

  • Page 8: Switch 2 (Sw2)

    The LEDs are used to indicate statuses, as listed below. Description POWER Lights when power is supplied to the RTE-V830-PC board. Lights when the CS0 pin of the CPU is active (low). Lights when the CS1 pin of the CPU is active (low).

  • Page 9: Serial Connector (Jsio)

    RTE-V830-PC USER’ S MANUAL 3.7. SERIAL CONNECTOR (JSIO) JSIO is a connector for the RS-232C interface controlled by the serial controller (SCC2691). It is a 9-pin D-SUB connector (D-SUB9) generally used with the PC/AT. All signals at this connector are at RS-232C level. Its pin arrangement and signal assignment are shown and listed below.

  • Page 10: Dram-Simm Sockets

    Section 6.2.) 3.11. ROM SOCKETS The RTE-V830-PC has ROM sockets to hold 40-pin ROM chips to provide standard 128 Kbytes (64K x 16 bits). When the ROM chips used here are to be replaced, the access time should be 150 ns or less.

  • Page 11: Installation And Use

    4. INSTALLATION AND USE The RTE-V830-PC board is designed to be installed in the ISA bus slot of a PC/AT or compatible (hereafter called the PC). However, it can also be used as a standalone, if it is powered from an external power supply.

  • Page 12: Installation On The Isa Bus

    INSTALLATION ON THE ISA BUS When the RTE-V830-PC is installed in the ISA bus slot of the PC, power (+5V) is supplied from the ISA bus to the board. In addition, the ISA bus can be used for communication with the debugger, so programs are down-loaded at high speed.

  • Page 13: Standalone Use Of The Board

    4.3. STANDALONE USE OF THE BOARD When the RTE-V830-PC is used as a standalone rather than being installed in the PC, it requires an external power supply. In addition, communication with the debugger is supported only by the RS-232C interface. This configuration is useful when the host debugger used with the board is not one in the PC/AT or compatible as well as when the board is used for hardware confirmation and expansion.

  • Page 14: Hardware References

    Memory Map DRAM spaces (0000-0000H to 01FF-FFFFH and 4000-0000H to 41FF-FFFFH) These are spaces in 72-pin SIMM chips mounted on the RTE-V830-PC board. Two 4-Mbyte SIMM chips are used in a standard configuration. They can be replaced with 8- or 16-Mbyte SIMM chips for memory expansion.

  • Page 15: I/O Map

    The standard ROM chip that is factory-set contains the Multi monitor. 5.2. I/O MAP The I/O space in the V830-CPU is not used by the RTE-V830-PC. The I/O registers used for control purposes are allocated in the memory-mapped SYSTEM-I/O space.

  • Page 16: System-I/O

    RTE-V830-PC USER’ S MANUAL 6. SYSTEM-I/O SYSTEM-I/O is an I/O device mapped in a memory space. The I/O devices include the UART/TIMER, PIO, and ISA bus interface. (No description about the ISA bus interface is included.) 6.1. UART/TIMER (SCC2691) The SCC2691 UART receiver/transmitter LSI chip produced by PHILIPS Signetics is used as the UART/TIMER.
  • Page 17 RTE-V830-PC USER’ S MANUAL Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PORT0 SRAMRD SRAMRD SRAMWR SRAMWR Reserved field 1 INTERLEAVE WIDE1 WIDE0 WIDE1 WIDE0 Output PORT1 PCWIDE1 PCWIDE0 RDCAS RDCAS WRCAS MINRASWIDE[2..0] WIDE1 WIDE0 WIDE0 Output PORT2 PD[2..1] TOVERF-...
  • Page 18 RTE-V830-PC USER’ S MANUAL Port 1: DRAM access condition setting output port (input)..61000804h PRCWIDE PRCWIDE RDCAS RDCAS WRCAS MINRAS MINRAS MINRAS WIDE1 WIDE0 WIDE0 WIDE2 WIDE1 WIDE0 MINRASWIDE2..0: These bits specify the minimum RAS width for DRAM operations. RASWIDE RASWIDE...
  • Page 19 RTE-V830-PC USER’ S MANUAL PRCWIDE1..0: These bits specify the precharge width for DRAM operations. PRCWIDE1 PRCWIDE0 Function This bit combination shall not be specified. The precharge width is specified to be one CPU bus clock cycle. The precharge width is specified to be two CPU bus clock cycles.

  • Page 20: Other Ports

    RTE-V830-PC USER’ S MANUAL PD[2] PD[1] DRAM capacity 4 Mbytes Reserved 16 Mbytes 8 Mbytes PD[2..1] and DRAM Capacity Ports 0 to 2: Control ports..6100080Ch Ports 0, 1, and 2 belong to the µPD71055. These ports are initialized by writing to the indicated location.
  • Page 21 RTE-V830-PC USER’ S MANUAL TIM1 TIM0 Timer rate No timer is used. 200 Hz ( 5 ms) 100 Hz (10 ms) 60 Hz (16.67 ms) CMODE: The multiplication factor for the internal clock frequency (triple for ON and double for OFF)

  • Page 22: Jext Bus Specification

    RTE-V830-PC USER’ S MANUAL 7. JEXT BUS SPECIFICATION The JEXT is a connector which is used to expand memory and I/O units. The local bus on this board is connected to the JEXT connector. The following tables list the pin arrangement of the JEXT connector and the functions of each signal.
  • Page 23 RTE-V830-PC USER’ S MANUAL A[0..19] A[0..19] BHE- BHE- High High D[0..15] Dout D[0..15] READY READY Read cycle Write cycle JEXT Bus Cycle Description Min. (ns) Max. (ns) Symbol RD address setup time RD address hold-up time RD cycle time RD cycle interval...

  • Page 24: Other Cpu Resources

    RTE-V830-PC USER’ S MANUAL 8. OTHER CPU RESOURCES 8.1. RESET- The factors listed below trigger a CPU reset. These factors reset the CPU. They also system-reset the board control circuit. Power-on reset: Occurs when the power to the board is switched on.

  • Page 25: Multi Monitor

    RTE-V830-PC USER’ S MANUAL 9. Multi MONITOR The ROM chip on the board is incorporated with the Multi monitor. The following cautions should be observed when the board is connected to the Multi server as the host. 9.1. MONITOR WORK RAM The monitor uses the first 64-KB area in the SRAM as work RAM.

  • Page 26: Rte Commands

    RTE-V830-PC USER’ S MANUAL RTE COMMANDS When the monitor and server are connected, the TARGET window is opened. The RTE commands can be issued in this window. The following table lists the RTE commands. Command Description HELP or ? Displays help messages.

  • Page 27: Outb, Outh, And Outw

    RTE-V830-PC USER’ S MANUAL 10.5. OUTB, OUTH, AND OUTW <Format> OUTB [[address] data] OUTH [[address] data] OUTW [[address] data] Write to an I/O register. The OUTB, OUTH, and OUTW commands access in byte, halfword, and word units, respectively. If an address or data is omitted, the previous address or data is assumed.

  • Page 28: Appendix Dram Timing

    RTE-V830-PC USER’ S MANUAL APPENDIX DRAM TIMING 11.1. DRAM INTERFACE OVERVIEW The DRAM consists of two 32-bit banks. In the ordinary mode (interleave mode), the banks are accessed alternately so that the access time during burst access can be reduced.

  • Page 29: 32-Bit Bus Mode (Single Read, Normal)

    RTE-V830-PC USER’ S MANUAL 11.3. 32-BIT BUS MODE (SINGLE READ, NORMAL) The following timing chart shows the waveforms that occur when an area is accessed in a single read cycle during the 32-bit bus mode for the first time after a reset or when the area is accessed after the precharge time has elapsed since the end of a refresh cycle (normal).

  • Page 30: 32-Bit Bus Mode (Single Read, Hit)

    RTE-V830-PC USER’ S MANUAL 11.4. 32-BIT BUS MODE (SINGLE READ, HIT) The following timing chart shows the waveforms that occur when a row address to be accessed in a single read cycle during the 32-bit bus mode matches (hit) a row address used in the previous cycle.

  • Page 31: 32-Bit Bus Mode (Single Read, Nohit)

    RTE-V830-PC USER’ S MANUAL 11.5. 32-BIT BUS MODE (SINGLE READ, NOHIT) The following timing chart shows the waveforms that occur when a row address to be accessed in a single read cycle during the 32-bit bus mode does not match (nohit) a row address used in the previous cycle.

  • Page 32: 32-Bit Bus Mode (Single Write, Normal)

    RTE-V830-PC USER’ S MANUAL 11.6. 32-BIT BUS MODE (SINGLE WRITE, NORMAL) The following timing chart shows the waveforms that occur when an area is accessed in a single write cycle during the 32-bit bus mode for the first time after a reset or when the area is accessed after the precharge time has elapsed since the end of a refresh cycle (normal).

  • Page 33: 32-Bit Bus Mode (Single Write, Hit)

    RTE-V830-PC USER’ S MANUAL 11.7. 32-BIT BUS MODE (SINGLE WRITE, HIT) The following timing chart shows the waveforms that occur when a row address to be accessed in a single write cycle during the 32-bit bus mode matches (hit) a row address used in the previous cycle.

  • Page 34: 32-Bit Bus Mode (Single Write, Nohit)

    RTE-V830-PC USER’ S MANUAL 11.8. 32-BIT BUS MODE (SINGLE WRITE, NOHIT) The following timing chart shows the waveforms that occur when a row address to be accessed in a single write cycle during the 32-bit bus mode does not match (nohit) a row address used in the previous cycle.

  • Page 35: 32-Bit Bus Mode (Burst Read, Interleave)

    RTE-V830-PC USER’ S MANUAL 11.9. 32-BIT BUS MODE (BURST READ, INTERLEAVE) The following timing chart shows the waveforms that occur when a DRAM area row address to be accessed in a burst read cycle in the 32-bit bus interleave mode matches (hit) a row address used in the previous cycle.

  • Page 36: 32-Bit Bus Mode (Burst Write, Interleave)

    RTE-V830-PC USER’ S MANUAL 11.10. 32-BIT BUS MODE (BURST WRITE, INTERLEAVE) The following timing chart shows the waveforms that occur when a DRAM area row address to be accessed in a burst write cycle during the 32-bit bus interleave mode matches (hit) a row address used in the previous cycle.

  • Page 37: 32-Bit Bus Mode (Burst Read, Noninterleave)

    RTE-V830-PC USER’ S MANUAL 11.11. 32-BIT BUS MODE (BURST READ, NONINTERLEAVE) The following timing chart shows the waveforms that occur when a DRAM area row address to be accessed in a burst read cycle during the 32-bit bus noninterleave mode matches (hit) a row address used in the previous cycle.

  • Page 38: 32-Bit Bus Mode (Burst Write, Noninterleave)

    RTE-V830-PC USER’ S MANUAL 11.12. 32-BIT BUS MODE (BURST WRITE, NONINTERLEAVE) The following timing chart shows the waveforms that occur when a DRAM area row address to be accessed in a burst write cycle during the 32-bit bus noninterleave mode matches (hit) a row address used in the previous cycle.

  • Page 39: 16-Bit Bus Mode (Single Read)

    RTE-V830-PC USER’ S MANUAL 11.13. 16-BIT BUS MODE (SINGLE READ) The byte-unit or halfword-unit single read access in the 16-bit bus mode is the same as that in the 32-bit bus mode. The word-unit single read access in the 16-bit bus mode behaves similarly to the burst mode, and differs from that in the 32-bit bus mode.
  • Page 40 RTE-V830-PC USER’ S MANUAL BCLK BCYST- Sig1 D0 to D15 Nclk READY- RAS- Nclk CASL- CASH- Sig1: A2 to A27, BE0- to BE3-, ST0 to ST3...

  • Page 41: 16-Bit Bus Mode (Single Write)

    RTE-V830-PC USER’ S MANUAL 11.14. 16-BIT BUS MODE (SINGLE WRITE) The byte-unit or halfword-unit single write access in the 16-bit bus mode is the same as that in the 32-bit bus mode. The word-unit single write access in the 16-bit bus mode behaves similarly to the burst mode, and differs from that in the 32-bit bus mode.

  • Page 42: 16-Bit Bus Mode (Burst Read, Interleave)

    RTE-V830-PC USER’ S MANUAL 11.15. 16-BIT BUS MODE (BURST READ, INTERLEAVE) The following timing chart shows the waveforms that occur when a DRAM area row address to be accessed in a burst read cycle during the 16-bit bus interleave mode matches (hit) a row address used in the previous cycle.

  • Page 43: 16-Bit Bus Mode (Burst Write, Interleave)

    RTE-V830-PC USER’ S MANUAL 11.16. 16-BIT BUS MODE (BURST WRITE, INTERLEAVE) The following timing chart shows the waveforms that occur when a DRAM area row address to be accessed in a burst write cycle during the 16-bit bus interleave mode matches (hit) a row address used in the previous cycle.

  • Page 44: 16-Bit Bus Mode (Burst Read, Noninterleave)

    RTE-V830-PC USER’ S MANUAL 11.17. 16-BIT BUS MODE (BURST READ, NONINTERLEAVE) The following timing chart shows the waveforms that occur when a DRAM area row address to be accessed in a burst read cycle during the 16-bit bus noninterleave mode matches (hit) a row address used in the previous cycle.

  • Page 45: 16-Bit Bus Mode (Burst Write, Noninterleave)

    RTE-V830-PC USER’ S MANUAL 11.18. 16-BIT BUS MODE (BURST WRITE, NONINTERLEAVE) The following timing chart shows the waveforms that occur when a DRAM area row address to be accessed in a burst write cycle during the 16-bit bus noninterleave mode matches (hit) a row address used in the previous cycle.
  • Page 46 RTE-V830-PC USER’ S MANUAL - Memo - RTE-V830-PC User’ s Manual M471MNL02 Midas lab...

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