Midas RTE-V852-PC User Manual
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Midas RTE-V852-PC User Manual

Midas RTE-V852-PC User Manual

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RTE-V852-PC
User' s Manual
(Rev. 1.10)
Midas lab

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  • Page 1 RTE-V852-PC User’ s Manual (Rev. 1.10) Midas lab...
  • Page 2 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) REVISION HISTORY Date of Revision Chapter Description enforcement August 15, 1996 1.00 First issue December 4, 1996 1.10 3. 5 Correction JPORT2 Pin Arrangement (P21,P21) Correction INT- of JEXT Connector Signals Correction INTP0(P24/INTP03) to INTP0(P22/INTP01)

  • Page 3: Table Of Contents

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) CONTENTS 1. INTRODUCTION ....................5 1.1. NUMERIC NOTATION ....................5 2. FEATURES AND FUNCTIONS ................6 3. BOARD CONFIGURATION................7 3.1. RESET SWITCH [SOCKET BOARD] (RESET_SW) ............ 7 3.2. RESET SWITCH [BASE BOARD] (SW_RESET) ............7 3.3.
  • Page 4 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 5. HARDWARE REFERENCES ................23 5.1 MEMORY MAP ......................23 6. SYSTEM-I/O..................... 25 6.1. SYSTEM-I/O LIST ..................... 25 6.2. UART/PRINTER (TL16C552A) (3F-F000H TO 3F-F026H) ......... 26 6.3. TIC (µPD71054) (3F-F030H TO 3F-F038H) ............... 28 6.4.
  • Page 5 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 11. RTE COMMANDS ..................46 11.1. HELP (?) ........................46 11.2. INIT.......................... 46 11.3. VER ......................... 46 11.4. SFR ......................... 46 12. APPENDIX BUS CYCLE................47 12.1. TIME-OVER READY....................47 12.2. DRAM INTERFACE ....................47 12.2.1.

  • Page 6: Introduction

    USER’ S MANUAL (Rev. 1.10) INTRODUCTION This manual describes the RTE-V852-PC, which is an evaluation board for the V852, NEC’ s CPU. With the RTE-V852-PC, it is possible to develop and debug programs, and evaluate the CPU performance, using the GreenHills Multi debugger. Communication with this debugger is carried out using the IBM-PC/AT ISA bus or RS-232C serial interface.

  • Page 7: Features And Functions

    USER’ S MANUAL (Rev. 1.10) 2. FEATURES AND FUNCTIONS The overview of each function block of the RTE-V852-PC is shown below. The RTE-V852-PC consists of the Socket board (smaller board) on which the CPU is mounted, and the Base board on which other components and the Socket board are mounted.

  • Page 8: Board Configuration

    USER’ S MANUAL (Rev. 1.10) 3. BOARD CONFIGURATION The physical layout of the major components on the RTE-V852-PC board is shown below. This chapter explains each component. To use the board with the Multi debugger, first read Chapter 4 before reading this chapter.

  • Page 9: Power Supply Connector [Scoket/Base Board] (Jpower)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 3.4. POWER SUPPLY CONNECTOR [SCOKET/BASE BOARD] (JPOWER) When this board is to be used as a standalone, that is, without being inserted in an ISA bus slot, the board should be supplied with power from an external power supply by connecting it to the JPOWER connector.

  • Page 10: Processor Pin Connectors [Socket Board]

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 3.5. PROCESSOR PIN CONNECTORS [SOCKET BOARD] (JPORT0, JPORT1, JPORT2, JPORT3, JPORT10) The pins of the CPU are inserted into these connectors. For details of the connections within the board, see Chapter 13. JPORT0 JPORT0...
  • Page 11 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 3.6. PROCESSOR PIN CONNECTORS [SOCKET BOARD/BASE BOARD] (J1, J2/J5, J6) These connectors are used to connect the Socket board to the Base board. J1/J5 pin No. Signal name J1/J5 pin No. Signal name P57/AD15...

  • Page 12: Serial Connector [Socket Board] (J3)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 3.7. SERIAL CONNECTOR [SOCKET BOARD] (J3) The J3 connector is used for the RS-232C interface, controlled by the UART built into the CPU. The pins of this connector have a pitch of 2.54 mm, and the pin arrangement is identical to that of the 9- pin D-SUB RS-232C connector normally provided on the PC/AT when using a push-fit connector with a ribbon cable.

  • Page 13: Switch 1 [Socket Board] (Sw1)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 3.8. SWITCH 1 [SOCKET BOARD] (SW1) SW1 on the Socket board is the switch used for setting the mode. SW1 contact Port MODE CKSEL PLLSEL P3MODE SW1-to-Port Correspondence MODE1: Switch for specifying the operation mode of the V852.

  • Page 14: 7-Segment Led [Socket Board] (Led_P1)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 3.11. 7-SEGMENT LED [SOCKET BOARD] (LED_P1) LED_P1 is a 7-segment LED, to which the P1 ports of the CPU are connected as shown in the table below. When a bit is set to 1, the corresponding segment lights.

  • Page 15: Switch 3 [Base Board] (Sw3)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 3.15. SWITCH 3 [BASE BOARD] (SW3) SW3 is the switch used for selecting whether the interrupt factors on the Base board are to be connected to the CPU. The relationship between the switch contact numbers, CPU interrupt pins and interrupt factors is given in the table below.

  • Page 16: Test Pins For Rom Emulation [Base Board] (Jromem)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 3.19. TEST PINS FOR ROM EMULATION [BASE BOARD] (JROMEM) JROMEM are the test pins used to connect a ROM in-circuit type debugger. These test pins accept control signals from the ROM in-circuit debugger. The signal names and functions are listed in the table below.

  • Page 17: Serial Connectors [Base Board] (Jsio1, Jsio2)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 3.20. SERIAL CONNECTORS [BASE BOARD] (JSIO1, JSIO2) The JSIO1 and JSIO2 connectors are used for the RS-232C interface controlled by the serial controller (TL16C552A). Regarding the connector shapes, JSIO1 is a 9-pin D-SUB RS-232C connector like that normally provided on the PC/AT, while JSIO2 is a pin header type connector with a pitch of 2.54 mm.

  • Page 18: Parallel Connector [Base Board] (Jprt)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 3.21. PARALLEL CONNECTOR [BASE BOARD] (JPRT) The JPRT connector is used for the parallel interface controlled by the parallel (printer) controller (TL16C552A). It is a pin header type connector with a pitch of 2.54 mm. All signals at this connector are at the RS-232C level.

  • Page 19: Dram-Simm Sockets

    SIMM can be read through the PIO port. (See Section 6.6.) 3.25. ROM SOCKETS The RTE-V852-PC has ROM sockets to hold 40-pin ROM chips to provide standard 128 Kbytes (64K × 16 bits). When the standard ROM is replaced to enable the use of a Multi debugger, connect ROM having an access time of no more than 150 ns.

  • Page 20: Installation And Use

    4. INSTALLATION AND USE The RTE-V852-PC board is designed to be installed in the ISA bus slot of a PC/AT or compatible (hereafter called the PC). However, it can also be used as a standalone, if it is powered from an external power supply.
  • Page 21 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) SW1 contact Profiler period Note Setting Timer is not used. 200 Hz 5 ms 100 Hz 10 ms 60 Hz 16.67 ms (factory-set) Note: Do not set this contact when using a Multi debugger. (See Section 10.5.)
  • Page 22 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) oscillator to JP1. When the clock must be changed, see Section 3.10.

  • Page 23: Installation On The Isa Bus

    4.2. INSTALLATION ON THE ISA BUS When the RTE-V852-PC is installed in the ISA bus slot of the PC, power (+5 V) is supplied from the ISA bus to the board. In addition, the ISA bus can be used for communication with the debugger, so programs are down-loaded at high speed.

  • Page 24: Hardware References

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 5. HARDWARE REFERENCES This chapter describes the hardware of the RTE-V852-PC. 5.1 MEMORY MAP The memory assignment of the board is shown below. As the CPU of the V852 includes built-in resources, the built-in resources appear in place of the external resources in those spaces where the built-in resources exist.
  • Page 25 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) ROM space (00-0000H to 07-FFFFH, 10-0000H to 17-FFFFH) This 512-Kbyte space is provided as ROM on the Base board. The standard ROM has a capacity of 256 Kbytes and an access time of no more than 150 ns. The ROM is capable of inserting wait states into the access cycle based on ready signal control, and the wait count can be set with SYSTEM-I/O (see Section 6.7).

  • Page 26: System-I/O

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 6. SYSTEM-I/O SYSTEM-I/O is an I/O device mapped in a memory space. The I/O devices include the UART/PRINTER, TIC, PIO, and ISA bus interface. (No description about the ISA bus interface is included.) 6.1. SYSTEM-I/O LIST The following table lists the SYSTEM-I/O functions.

  • Page 27: Uart/Printer (Tl16C552A) (3F-F000H To 3F-F026H)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 6.2. UART/PRINTER (TL16C552A) (3F-F000H TO 3F-F026H) The TL16C552A (dual asynchronous communications element with FIFO) IC produced by Texas Instruments is used as UART/PRINTER. The TL16C552A has two UART channels and one channel of the bidirectional printer board. It incorporates a 16-character FIFO buffer in the UART reception circuitry to minimize the possibility of an overrun error during reception.
  • Page 28 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) The UART-CH#1, UART-CH#2 and PRINTER interrupts can be connected to the CPU's interrupt ports as shown in the following table. Interrupt source Interrupt to connected CPU UART-CH#1 NMI- , P22/INTP01 UART-CH#2 NMI- , P21/INTP00...

  • Page 29: Tic (Μpd71054) (3F-F030H To 3F-F038H)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 6.3. TIC (µPD71054) (3F-F030H TO 3F-F038H) The µPD71054 produced by NEC is installed as a TIC. The µPD71054 is compatible with the i8254 produced by Intel. It has three timers/counters. These timers/counters are used to generate the DRAM refresh timing and monitor timer interrupts.

  • Page 30: 7-Segment Led Display Data Output Port (3F-F040H [Write Only])

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 6.4. 7-SEGMENT LED DISPLAY DATA OUTPUT PORT (3F-F040H [Write Only]) This port sets the data to be displayed on the 7-segment LED on the Base board. The data format is as shown in table below. Setting a bit to 0 causes the corresponding segment to light.

  • Page 31: Status Read Port (3F-F060H [Read Only])

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) TIM1 TIM0 Timer rate Timer not used 200 Hz (5 ms) 100 Hz (10 ms) 60 Hz (16.67 ms) 6.6. STATUS READ PORT (3F-F060H [READ ONLY]) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0...

  • Page 32: Bic (Bus Interface Control) (3F-F080H To 3F-F0F0H)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 6.7. BIC (BUS INTERFACE CONTROL) (3F-F080H TO 3F-F0F0H) The BIC is used to set the parameters related to access to ROM, SRAM, DRAM and the ports on the Base board. Address Bit7 Bit6 Bit5 Bit4 Bit3...

  • Page 33: Nmi Select Port (3F-F140H To 3F-F150H)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) PAGEMODE Function DRAM is not used in page mode. DRAM is used in page mode. This is reset to [0] when the system is reset. SYSIOWAIT1 SYSIOWAIT0 Function (Sets the wait count for SYSTEM-I/O access to 8.) Sets the wait count for SYSTEM-I/O access to 1.
  • Page 34 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) Reserved (0): This bit is reserved and should be set to “ 0” .

  • Page 35: Nmi Status Port (3F-F160H To 3F-F170H [Read Only])

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 6.9. NMI STATUS PORT (3F-F160H TO 3F-F170H [READ ONLY]) This port is used to identify the source of an NMI request. See Section 9.2 for details of the NMI signal generation logic. Address Bit7 Bit6 Bit5 Bit4...

  • Page 36: Int0(P22/Intp01) Select Port (3F-F200H)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 6.12. INT0(P22/INTP01) SELECT PORT (3F-F200H) This port controls the generation of the INT0(P22/INTP01) signal. See Section 9.3 for details of the INT0 signal generation logic. Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0...

  • Page 37: Int1 (P24/Intp03) Status Port (3F-F230H [Read Only])

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 6.15. INT1 (P24/INTP03) STATUS PORT (3F-F230H [READ ONLY]) This port is used to identify the source of an INT1 (P24/INTP03) request. See Section 9.3 for details of the INT0 signal generation logic. Address Bit7 Bit6 Bit5 Bit4 Bit3...

  • Page 38: Recommended Settings

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 7. RECOMMENDED SETTINGS This chapter specifies the recommended values for the parameters related to access to memory resources. 7.1. CPU SETTING No restrictions are imposed on the settings of the bus control function built into the CPU. Therefore, to maximize the bus performance, set DWC (0xFFFF to F060) of SFR to 0x0000 and BCC (0xFFFF to F062) to 0x0000.
  • Page 39 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) Therefore, generate the DIPSW1 read port read cycles the number of times specified in the table below, immediately after accessing the TL16C552A or µPD71054. DIPSW1 read port read cycle SYSTEM-I/O command recovery time Two times (independent of the CPU operating...

  • Page 40: Jext Bus Specification

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 8. JEXT BUS SPECIFICATION The JEXT is a connector which is used to expand memory and I/O units. The local bus on this board is connected to the JEXT connector. The following tables list the pin arrangement of the JEXT connector and the functions of each signal.
  • Page 41 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) A[0..19] A[0..19] BHE- BHE- High High Dout D[0..15] D[0..15] READY READY Read cycle Write cycle JEXT Bus Cycle Symbol Description Min. (ns) Max. (ns) RD address setup time RD address hold-up time RD cycle time...

  • Page 42: Other Cpu Resources

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 9. OTHER CPU RESOURCES 9.1. RESET- The factors listed below trigger a CPU reset. These factors reset the CPU. They also system-reset the board control circuit. • Power-on reset: Occurs when the power to the board is switched on.
  • Page 43 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) • NMI request from JROMEM: NMI is generated by the input to the NMI pin of the JROMEM connector on the Base board. See Section 3.19 for details. • Request received from ISA bus: NMI can be used for controlling communications via the ISA bus.

  • Page 44: Maskable Interrupts (Int0(P22/Intp01), Int1 (P24/Intp03))

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 9.3. MASKABLE INTERRUPTS (INT0(P22/INTP01), INT1 (P24/INTP03)) The factors listed below trigger INT0 (P00/INTP00). See Section 6.12 for details of selecting an interrupt. • Request from controller on the Base board: INT0 (P22/INTP01) can be generated by the UART-CH#1 or PRINTER interrupt request received from the UART/PRINT controller (TL16C552A) on the Base board (see Section 6.2).

  • Page 45: Port

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) The figure below outlines the INT0/INT1 generation logic. UART1_INT0 INT0_MASK UART1_INT0EN ISACOM_INT0 P22/INTP01 To CPU ISACOM_INT0EN SW3-2 PRT_INT0 PRT_INT0EN TIMER_INT1 INT1_MASK TIMER_INT1 P24/INTP03 To CPU TOVER_INT1 SW3-4 TOVER_INT1 9.4. PORT Among the CPU ports, P4[0..7], P5[0..7], P6[0..3] and P9[0..6], which are related to the external extension bus, are used for connection to the Base board.

  • Page 46: Multi Monitor

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 10. Multi MONITOR The ROM chip on the board is incorporated with the Multi monitor. The following cautions should be observed when the board is connected to the Multi server as the host. 10.1. MONITOR WORK RAM The monitor uses the first 32-KB (1F-8000H to 1F-EFFFH) area in the SRAM as work RAM.

  • Page 47: Rte Commands

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 11. RTE COMMANDS When the monitor and server (rteserv) are connected, the TARGET window is opened. The RTE commands can be issued in this window. The following table lists the RTE commands. Command Description HELP or ? Displays help messages.

  • Page 48: Appendix Bus Cycle

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 12. APPENDIX BUS CYCLE 12.1. TIME-OVER READY On the Base board, when an external bus cycle generated by the CPU has not been completed within a certain period, the time-over ready status is generated to forcibly complete the cycle. Time-over ready is generated when a bus cycle has been generated continuously for 1024 clocks (approx.

  • Page 49: Single Read (Normal Mode)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 12.2.3. Single Read (Normal Mode) In normal mode, read cycles always occur as single read cycles, as shown in the following timing chart. • In this timing chart, two read cycles are generated successively after the completion of RAS precharge of the previous cycle.

  • Page 50: Single Write (Normal Mode)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 12.2.4. Single Write (Normal Mode) In normal mode, write cycles always occur as single write cycles, as shown in the following timing chart. • In this timing chart, two write cycles are generated successively after the completion of RAS precharge of the previous cycle.

  • Page 51: Page Access (Page Mode, Same Row Address)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 12.2.5. Page Access (Page Mode, Same Row Address) In the page mode cycle, continuous access to the same row address is performed by controlling only the CAS signal while keeping the RAS signal active, as shown in the following timing chart.

  • Page 52: Page Access (Page Mode, Different Row Addresses)

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 12.2.6. Page Access (Page Mode, Different Row Addresses) When a different row address from the previously-accessed row address is accessed in page mode, the RAS signal is deactivated from the start of the cycle and activated again after having waited for a period equal to the RAS signal precharge time, as shown in the following timing chart.

  • Page 53: Appendix Cpu Port Connections

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 13. APPENDIX CPU PORT CONNECTIONS This chapter describes the connection schemes of the CPU ports which are connected to the connectors on the Socket board. 13.1. P00 TO P07 47 kΩ JPORT0 P0[0:7] 13.2. P10 TO P17 47 k Ω...

  • Page 54: P30 To P37

    RTE-V852-PC USER’ S MANUAL (Rev. 1.10) 13.4. P30 TO P37 47 kΩ JPORT3 P3[1,2,3] P3[5] 47 k Ω P3[4,6,7] 232C Driver Buf. P3MODE 13.5. P100 TO P103 47 kΩ JPRT10 P10[0:3]...
  • Page 55 RTE-V852-PC USER’ S MANUAL (Rev. 1.10) - Memo - RTE-V852-PC User’ s Manual M662MNL02 Created on August 15, 1996. Rev. 1.00 Midas lab...

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