ROHS QSM-622E User Manual page 46

BIOS
3.3.2.3 PCI Express Configuration
Item
PCI Express Port
0/1/2/3
Hot Plug
Speed
Extra Bus Reserved
Reserved Memory
Reserved Memory
Alignment
Perfetchable Memory
Perfetchable Memory
Alignment
Reserved I/O
Description
Enable (default) or Disable PCI Express Port
0/1/2/3 in the chipset.
Enable (default) or Disable PCI Express Hot plug.
Configure PCIe Port Speed.
Options: Auto (default), Gen 2 and Gen 1.
►
Extra Bus Reserved for bridges behind this Root
Bridge.
Options: 0~3 (Default: 1 for PCI Express port 0,
►
0 for PCI Express port 1/2/3)
Reserved Memory Range for this Root Bridge.
Default: 10
Reserved Memory Alignment (0~31 bits).
Default: 1
Perfetchable Memory Range for this Root Bridge.
Default: 10
Perfetchable Memory Alignment (0~31 bits).
Default: 1
Reserved I/O Range for this Root Bridge.
Default: 4
- 36 -