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7. CIRCUIT DIAGRAM
1
2
For ECM MIC Test
MICBIAS
C100
NA
A
MIC_ABB_P
NA
C101
MIC_ABB_N
B
VRSIM
MEGA SIM SOCKET
R109
V_28
R110
0
10
R114
NA
4
MEGA_DAT0_28
R116
24
3
C
SIM_CLK
2
SIM_RST
1
C120
C121
0.1u
C123
150p
150p
D
VBAT
MAIN_KEY_BL_EN
E
1
2
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3
4
5
L100
100nH
100nH
L101
C102
MIC100
1
0.1u
OUT
2
C104
G1
3
G2
4
100nH
0.1u
ZD100
PWR
5
L102
G3
27p
C109
1uF
SP0204LE5-PB
27p
C107
GRM36Y5V105Z6.3PT
C110
C111
100p
10u
VA100
EVLC14S02050
NOT MOUNT
VBAT
U100 R1114D281D-TR-F
1
3
VDD
VOUT
4
2
NC
GND1
NA
6
5
CE
GND2
C113
NA
C114
NA
R111
NA
J100
R113
10K
9
SIM_PWRCTRL
GND2
GND1
8
R115
NA
MMC_DAT
MMC_CMD
MEGA_CMD_28
7
UCLK
UIO
SIM_IO
6
R118
NA
URST
VPP_MMC_CLK
MEGA_CLK_28
5
VDD
GND
C122
22p
VBAT
BATTERY TERMINAL
CN100
VBATS
3
BATT_TEMP
2
4
1
C125
10u
3
4
5
6
7
BLUETOOTH (Shielding Block)
VBAT
C103
C105
1u
0.1u
D7
BT_CLK_REQ
IO0_EXT_CLK_REQ_OUT
C6
IO1_EXT_CLK_REQ_IN
KA_OUT
B7
IO2_SCL
ANA_OUT
RFIO_OUT
D5
IO3_SDA
A6
IO4
C4
IO5
C8
IO7
B4
SYSCLKEN
IO14
F7
IO15
F2
RFIO_LDO_OUT
G3
OSC_LDO_OUT
G4
TL_LDO_OUT
D2
ANA_LDO_OUT
A4
BB_LDO_OUT1
H5
BB_LDO_OUT2
F8
BB_LDO_OUT3
C115
C116
C117
C118
0.1u
4.7u
0.1u
1u
Connect the digital and analog ground in the 4 layer, do not connect on the top layer
RF_P
SC100
1
8
2
7
3
6
4
5
RF_M
- 121 -
8
9
10
VRIO
KA_OUT
VLDO_OUT
10K
R102
VLDO_OUT
C106
4.7u
C108
CLK_32K
47p
ANA_OUT
H1
RFP
RF_P
H2
RFM
RF_M
C3
JTAG_TDI
E6
JTAG_TDO
B5
JTAG_TMS
D4
JTAG_TCK
E5
HCI_TX
BT_RX
E4
U101
HCI_RX
BT_TX
E8
HCI_CTS
BT_RTS
E7
BRF6150HZSL
HCI_RTS
BT_CTS
R108
820
C112
0.1u
E2
XTALP_FAST_CLK_IN
BT_CLK
E1
XTALM
C5
AUD_IN
MCSI1_DOUT
A7
AUD_FSYNC
MCSI1_SYNC
C7
AUD_OUT
MCSI1_DIN
B6
AUD_CLK
MCSI1_BCLK
C119
Delete R120 after PV EVENT
TP100
1u
UART_TXD
RFIO_OUT
DBF81H903 FB100
6
1
GND1
NC
ANT100
ANT101
5
2
R119
0
BL2
DC
4
3
BL1
UNBL
R120
R121
C124
NA
NA
100p
LGMC
LGE Internal Use Only
A
B
C
D
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