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3 Block Diagrams
3.1.
CCD DRIVE BLOCK DIAGRAM
CCD DRIVE BLOCK DIAGRAM
CCD P.C.B.
IC601 (CCD)
CCD
Q601
IMAGE
7
BUFFER
SENSOR
V1
4
V2
3
V3
2
V4
1
SUB
10
RESET
9
H1
12
H2
13
MAIN P.C.B
IC302 (CAMERA SIGNAL PROCESS/TIMING GENERATOR)
FP31
53
CDS
PGA
1
IC303 (CCD V-DRIVE)
LEVEL
7
37
V1 PULSE
CHANGE
FP31
5
DRIVE
3
LEVEL
8
44
CHARGE PULSE 1
FP31
CHANGE
4
LEVEL
FP31
3
9
39
V2 PULSE
CHANGE
5
FP31
LEVEL
14
38
V3 PULSE
6
CHANGE
FP301
17
DRIVE
LEVEL
14
CHARGE PULSE 2
13
45
CHANGE
LEVEL
18
12
40
V4 PULSE
CHANGE
LEVEL
1
10
48
SUB CONTROL PULSE
CHANGE
FP31
35
RESET PULSE
10
FP31
31
H1 PULSE
13
FP31
32
H2 PULSE
12
6
9
10BIT A/D
CAMERA DATA (10 BIT)
11
CONVERTER
16
64
2
SERIAL INTERFACE
1
3
CG RESET (L)
19
FCK
24
VD
29
HD
28
X301
36MHz
XOUT
23
OSC
XIN
22
12MHz CLOCK
17
13
SDR-H18P / SDR-H20P / SDR-H18PC / SDR-H20PC
REC VIDEO(CAMERA) SIGNAL
TO VIDEO SIGNAL PROCESS
CAMERA DATA (0-9)
BLOCK DIAGRAM
CAMERA AFE CS (L)
CG/AFE SERIAL CLOCK
TO SYSTEM CONTROL
CG/AFE SERIAL DATA
BLOCK DIAGRAM
CG CS (L)
CG RESET (L)
V1
2.85 Vp-p
FCK (18.0MHz)
CAM VD
CAM HD
1 V
5 ms
TO VIDEO SIGNAL PROCESS
BLOCK DIAGRAM
12MHz CLOCK
CCD DRIVE BLOCK DIAGRAM
SDR-H18P/SDR-H18PC/SDR-H20P/SDR-H20PC
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