Keyboard; Input And Output Port - Radio Shack TRS-80 Reference Handbook

Keyboard
The TRS-80 Keyboard consists of 53 single-pole,
single-throw normally open keys molded in a
plastic base. The base is mounted, together with
four ICs and associated resistors, to the key-
board PCB. As you can see from the Schematic,
this Keyboard does not output ASCII. It is scan-
ned, like calculator-type keyboards. Each key
represents a switch across a matrix node. When
closed, the switch will short out a horizontal
line to a vertical line. ROM software will detect
the node short and generate ASCII equivalents
for that particu lar key.
The Keyboard is accessed by decoder signal
KYBD*. When this signal goes low, it enables
tristate buffers Z3 and Z4. The inputs to these
buffers are normally held high by the pull-up
resistors (at the top of the keyboard schematic)
R1 through R8. All of the horizontal address
lines are made to go high at the same time as
KYBD* goes low. If the CPU detects a logical
Ill" on one of the data lines, there is a key
pressed on the Keyboard. The CPU ROM will
then scan the address lines one-by-one until it
finds the "1" output on the data bus again.
After finding it, the ROM can instruct the CPU
how to generate the ASCII code for that parti-
cular key. At this time, the CPU also checks the
status of the two shift keys. If neither of these
keys is pressed, the ASCII code is not modified.
If a shift key is pressed, the ASCII is modified
accordingly.
Only one point should be brought up about the
Keyboard. The inverters on the address lines are
open-collector types. You may not be able to
see the address signal on Zl or Z2's output
unless one of the keys associated with that out-
put is pressed. With no key pressed, there is no
voltage applied to the KR (Keyboard Row)
lines. When a key is pressed, the associated pull-
up resistor supplies voltage. Then you will be
able to see activity on a KR line.
44
Input and Output Port
As you know by now, the TRS-80 microcom-
puter system is Memory Mapped. But it does
have input/output ports. The basic difference in
memory mapping and ports is in the method
data is handled. In memory mapping, the CPU
knows where the data is. In a port, the CPU does
not know and couldn't care where the data
is
located. If the port is some kind of memory,
the CPU will output data to that port; and it
would be up to port circuitry to process and
store data. In the input condition, the CPU
accesses the input port; and it is up to the port
to find data and feed th is data to the data bus
for the CPU.
The Z-80 CPU can access up to 256 output/
input ports. In the TRS-80 Level
I
system, we
only use one. The Cassette Recorder is the only
port used. Its
add~ess
is FF in hex. (Ports are
accessed using only the lower eight address
lines.)
Port Addressing
Since the TRS-80 uses only one output/input
port, there must be only one port decoder. The
port decoder is shown on Schematic Sheet 2,
between the Sync Mixing circuit and the Power
Supply.
Z54 monitors address bits Zl through Z7. Z52,
pin 5 monitors the Af/J line. When hex FF is
outputted on address lines Af/J through A7, Z54
pin 8, and Z52 pin 6, will go low. These two
outputs are tied to OR gate Z36, pins 2 and 1.
When A0* and FE* are low, FF* at pin
3
of
Z36 will go low. The port address decoding is
now complete. If we have a low at OUT* (the
CPU wants to access an output port when this
signal is low), Z25, pin 8 will output OUTSIG*
because OUT* and FF* are low. If we have a
low at
I
N* (the
CPU
wants to access an input