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Diamond Systems ZIRCON-MM User Manual

Pc/104 format i/o module with 8 analog inputs, 1 analog output, 24 digital i/o lines, 3 16-bit counter/timers (dx version), 1 interrupt line
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ZIRCON-MM
8-Bit Resolution Analog & Digital I/O
PC/104 Module
User Manual V2.11
© Copyright 2002
Diamond Systems Corporation
8430-D Central Ave.
Newark, CA 94560
Tel (510) 456-7800
Fax (510) 45-7878
techinfo@diamondsystems.com
www.diamondsystems.com

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  • Page 1 ZIRCON-MM 8-Bit Resolution Analog & Digital I/O PC/104 Module User Manual V2.11 © Copyright 2002 Diamond Systems Corporation 8430-D Central Ave. Newark, CA 94560 Tel (510) 456-7800 Fax (510) 45-7878 techinfo@diamondsystems.com www.diamondsystems.com...

  • Page 2: Table Of Contents

    TABLE OF CONTENTS 1. General Description ......................3 2. ZIRCON-MM I/O Header Pinout.................... 4 3. Base Address Configuration....................5 4. Interrupt Configuration ......................5 5. Analog I/O Configuration....................... 6 6. Zircon-MM Board Drawing ....................8 7. Register Map ........................9 8.

  • Page 3: General Description

    1. GENERAL DESCRIPTION ZIRCON-MM is a PC/104 format I/O module with 8 analog inputs, 1 analog output, 24 digital I/O lines, 3 16-bit counter/timers (DX version), and 1 interrupt line. Both the analog input and output resolution are 8 bits (1/256). The analog circuitry requires no calibration over the lifetime of the product.

  • Page 4: Zircon-Mm I/O Header Pinout

    2. ZIRCON-MM I/O HEADER PINOUT J3 is the I/O header for Zircon-MM. It is a standard 50-pin dual row male header. Analog In 7 Analog In 6 Analog In 5 Analog In 4 Analog In 3 Analog In 2 Analog In 1...

  • Page 5: Base Address Configuration

    Only one resistor should be connected to any interrupt line on the bus. Interrupts on Zircon-MM are driven by a tristate driver. When an interrupt is pending, the interrupt line is driven high, and when it is not pending, the output is in high-impedance mode, and the 1KΩ...

  • Page 6: Analog I/O Configuration

    For ZMM-DX, both jumpers should be in the left positions (over the middle and left pins). Do not alter the positions of these jumpers, since doing so will prevent the board from functioning properly. ZIRCON-MM User Manual v2.11 © 2002 Diamond Systems Corporation P. 6...
  • Page 7 Analog I/O Configuration Settings Input range Output range 0-2.5V 0-2.5V +/-2.5V +/-2.5V 0-1.25V 0-1.25V +/-1.25V +/-1.25V 0-5V 0-2.5V +/-5V +/-2.5V 0-2.5V 0-1.25V +/-2.5V +/-1.25V These are the only valid settings for ZMM-LC. ZIRCON-MM User Manual v2.11 © 2002 Diamond Systems Corporation P. 7...

  • Page 8: Zircon-Mm Board Drawing

    6. ZIRCON-MM BOARD DRAWING This drawing will help to locate various key features on the board as described in the configuration sections above. ZIRCON-MM User Manual v2.11 © 2002 Diamond Systems Corporation P. 8...

  • Page 9: Register Map

    A/D, D/A, Control, and Status register definitions are shown starting on the next page. For digital I/O and counter/timer register definitions, refer to the 82C55 and 82C54 datasheets, respectively. Counter/timers are not available on model ZMM-LC. ZIRCON-MM User Manual v2.11 © 2002 Diamond Systems Corporation P. 9...

  • Page 10: Register Definitions

    Base + 2 or 3: Start A/D Conversion (Write only) Both these addresses map to the same physical register on the board. Writing to this register starts an A/D conversion. The value written does not matter. ZIRCON-MM User Manual v2.11 © 2002 Diamond Systems Corporation P. 10...
  • Page 11 A/D Range selection from configuration header J4; see page 7 for details on the meaning of this bit TrigE, TrigC Readback of these control register bits (see above) Ch2, Ch1, Ch0 Readback of these control register bits (see above) ZIRCON-MM User Manual v2.11 © 2002 Diamond Systems Corporation P. 11...
  • Page 12 Input Input (all ports input) Input Input Output Input Output Input Input Output Output Output Input Input Output Input Output Output Output Input Output Output Output (all ports output) ZIRCON-MM User Manual v2.11 © 2002 Diamond Systems Corporation P. 12...

  • Page 13: Digital I/O Operation

    9. DIGITAL I/O OPERATION Addresses 8 – 11 on the board map to the 82C55 digital I/O chip on Zircon-MM. This chip provides 3 8-bit ports, called A, B, and C, for a total of 24 I/O lines. The chip contains four registers, 1 each for A, B, and C and 1 for control.

  • Page 14: Counter/Timers (Zmm-Dx Only)

    Then A/D conversions are initiated. Counter 0 is completely independent. All three control pins are available on the I/O header. Input and gate pins are connected to +5V through 10KΩ pull-up resistors. ZIRCON-MM User Manual v2.11 © 2002 Diamond Systems Corporation P. 14...

  • Page 15: Analog I/O

    Zircon-MM therefore requires no calibration over its entire operating lifetime. The analog I/O can be set to several different ranges, depending on the model of Zircon-MM. For model ZMM-LC, the analog circuitry is powered from the system +5/Ground supplies, so all analog I/O is limited to positive voltages (0 - 2.5V or 0 - 1.25V ranges).

  • Page 16: Analog Input Formulas

    The table below shows how to calculate the output code needed to generate the desired output voltage for each output voltage range on Zircon-MM. The output code is the 8-bit value written to the D/A converter. Converting Desired Output Voltages to D/A Converter Codes...

  • Page 17: Specifications

    0 - 70 +5VDC ±10% Power supply Current consumption ZMM-DX: 127mA (typical, all outputs open) ZMM-LC: 100mA PC/104 bus 8-bit bus used; 16-bit header footprint on board for passthrough ZIRCON-MM User Manual v2.11 © 2002 Diamond Systems Corporation P. 17...

  • Page 18: Gate

    82C54 S E M I C O N D U C T O R CMOS Programmable Interval Timer March 1997 Features Description • 8MHz to 12MHz Clock Input Frequency The Harris 82C54 is a high performance CMOS Programma- ble Interval Timer manufactured using an advanced 2 micron •...

  • Page 19: Gate

    82C54 Ordering Information PART NUMBERS TEMPERATURE 8MHz 10MHz 12MHz RANGE PACKAGE PKG. NO. CP82C54 CP82C54-10 CP82C54-12 C to +70 24 Lead PDIP E24.6 IP82C54 IP82C54-10 IP82C54-12 C to +85 24 Lead PDIP E24.6 CS82C54 CS82C54-10 CS82C54-12 C to +70 28 Lead PLCC N28.45 IS82C54 IS82C54-10...
  • Page 20 82C54 Pin Description (Continued) DIP PIN SYMBOL NUMBER TYPE DEFINITION CLK 2 CLOCK 2: Clock input of Counter 2. A0, A1 19 - 20 ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write operations. Normally connected to the system address bus. SELECTS Counter 0 Counter 1...
  • Page 21 82C54 Control Word Register The Control Word Register (Figure 2) is selected by the INTERNAL BUS Read/Write Logic when A1, A0 = 11. If the CPU then does a write operation to the 82C54, the data is stored in the Con- CONTROL STATUS trol Word Register and is interpreted as a Control Word used...
  • Page 22 82C54 Operational Description SC - Select Counter General After power-up, the state of the 82C54 is undefined. The Select Counter 0 Mode, count value, and output of all Counters are undefined. Select Counter 1 How each Counter operates is determined when it is pro- Select Counter 2 grammed.
  • Page 23 82C54 Possible Programming Sequence explained later. The second is a simple read operation of the (Continued) Counter, which is selected with the A1, A0 inputs. The only requirement is that the CLK input of the selected Counter must be inhibited by using either the GATE input or external LSB of Count - Counter 1 logic.
  • Page 24 82C54 1. Read least significant byte. The read-back command may also be used to latch status information of selected counter(s) by setting STATUS bit D4 2. Write new least significant byte. = 0. Status must be latched to be read; status of a counter is 3.
  • Page 25 82C54 Both count and status of the selected counter(s) may be If a new count is written to the Counter it will be loaded on the next CLK pulse and counting will continue from the new latched simultaneously by setting both COUNT and STATUS bits D5, D4 = 0.
  • Page 26 82C54 Mode 1: Hardware Retriggerable One-Shot Mode 2: Rate Generator OUT will be initially high. OUT will go low on the CLK pulse This Mode functions like a divide-by-N counter. It is typically following a trigger to begin the one-shot pulse, and will remain used to generate a Real Time Clock Interrupt.
  • Page 27 82C54 Mode 3: Square Wave Mode Mode 3 is Implemented as Follows: Mode 3 is typically used for Baud rate generation. Mode 3 is EVEN COUNTS: OUT is initially high. The initial count is similar to Mode 2 except for the duty cycle of OUT. OUT will loaded on one CLK pulse and then is decremented by two initially be high.
  • Page 28 82C54 CW = 18 LSB = 3 CW = 1A LSB = 3 GATE GATE CW = 18 LSB = 3 CW = 1A LSB = 3 GATE GATE CW = 18 LSB = 3 LSB = 2 CW = 1A LSB = 3 LSB = 5 GATE GATE...
  • Page 29 82C54 Counter New counts are loaded and Counters are decremented on MODE MIN COUNT MAX COUNT the falling edge of CLK. The largest possible initial count is 0; this is equivalent to 2 for binary counting and 10 for BCD counting. The counter does not stop when it reaches zero.
  • Page 30 82C55A CMOS Programmable Peripheral Interface June 1998 Features Description • Pin Compatible with NMOS 8255A The Intersil 82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a • 24 Programmable I/O Pins self-aligned silicon gate CMOS process (Scaled SAJI IV). It is a general purpose programmable I/O device which may be •...
  • Page 31 82C55A Pin Description SYMBOL NUMBER TYPE DESCRIPTION : The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is recommended for decoupling. GROUND D0-D7 27-34 DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus.
  • Page 32 82C55A Functional Description PA7- POWER GROUP A Data Bus Buffer GROUP A PORT A SUPPLIES CONTROL This three-state bi-directional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or PC7- received by the buffer upon execution of input or output GROUP A PORT C BI-DIRECTIONAL...
  • Page 33 82C55A Ports A, B, and C register will contain 9Bh. During the execution of the system program, any of the other modes may be selected using a The 82C55A contains three 8-bit ports (A, B, and C). All can single output instruction. This allows a single 82C55A to be configured to a wide variety of functional characteristics service a variety of peripheral devices with a simple software by the system software but each has its own special features...
  • Page 34 82C55A The modes for Port A and Port B can be separately defined, This function allows the programmer to enable or disable a while Port C is divided into two portions as required by the CPU interrupt by a specific I/O device without affecting any Port A and Port B definitions.
  • Page 35 82C55A Mode 0 (Basic Input) INPUT CS, A1, A0 D7-D0 Mode 0 (Basic Output) D7-D0 CS, A1, A0 OUTPUT Mode 0 Configurations CONTROL WORD #0 CONTROL WORD #2 PA7 - PA0 PA7 - PA0 82C55A 82C55A PC7 - PC4 PC7 - PC4 D7 - D0 D7 - D0 PC3 - PC0...
  • Page 36 82C55A Mode 0 Configurations (Continued) CONTROL WORD #4 CONTROL WORD #8 PA7 - PA0 PA7 - PA0 82C55A 82C55A PC7 - PC4 PC7 - PC4 D7 - D0 D7 - D0 PC3 - PC0 PC3 - PC0 PB7 - PB0 PB7 - PB0 CONTROL WORD #5 CONTROL WORD #9...
  • Page 37 82C55A Mode 0 Configurations (Continued) CONTROL WORD #12 CONTROL WORD #14 PA7 - PA0 PA7 - PA0 82C55A 82C55A PC7 - PC4 PC7 - PC4 D7 - D0 D7 - D0 PC3 - PC0 PC3 - PC0 PB7 - PB0 PB7 - PB0 CONTROL WORD #13 CONTROL WORD #15...
  • Page 38 82C55A tSIB tSIT tRIB INTR tRIT INPUT FROM PERIPHERAL FIGURE 7. MODE 1 (STROBED INPUT) INTR (Interrupt Request) INTE A A “high” on this output can be used to interrupt the CPU Controlled by Bit Set/Reset of PC6. when and input device is requesting service. INTR is set by INTE B the condition: STB is a “one”, IBF is a “one”...
  • Page 39 82C55A tWOB tAOB INTR tWIT tAIT OUTPUT FIGURE 9. MODE 1 (STROBED OUTPUT) PA7-PA0 PA7-PA0 STBA OBFA CONTROL WORD CONTROL WORD IIBFA ACKA D3 D2 D1 D0 D3 D2 D1 D0 INTRA INTRA PC6, PC7 PC4, PC5 PC6, PC7 PC4, PC5 1 = INPUT 1 = INPUT PB7, PB0...
  • Page 40 82C55A CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 INTRA 1/0 1/0 PA7-PA0 OBFA INTE ACKA PC2-PC0 1 = INPUT 0 = OUTPUT INTE STBA PORT B 1 = INPUT 0 = OUTPUT IBFA GROUP B MODE 0 = MODE 0 1 = MODE 1 PC2-PC0 FIGURE 11.
  • Page 41 82C55A MODE 2 AND MODE 0 (INPUT) MODE 2 AND MODE 0 (OUTPUT) INTRA INTRA PA7-PA0 PA7-PA0 OBFA OBFA CONTROL WORD CONTROL WORD ACKA ACKA D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 STBA STBA PC2-PC0 PC2-PC0...
  • Page 42 82C55A MODE DEFINITION SUMMARY MODE 0 MODE 1 MODE 2 GROUP A ONLY Mode 0 or Mode 1 Only INTRB INTRB IBFB OBFB STBB ACKB INTRA INTRA INTRA STBA STBA IBFA IBFA ACKA ACKA OBFA OBFA Special Mode Combination Considerations INPUT CONFIGURATION There are several combinations of modes possible.
  • Page 43 82C55A Applications of the 82C55A Reading Port C Status (Figures 15 and 16) In Mode 0, Port C transfers data to or from the peripheral The 82C55A is a very powerful tool for interfacing peripheral device. When the 82C55A is programmed to function in equipment to the microcomputer system.

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