Pnx2015: Columbus (Comb Filter); Pnx2015: Hd Subsystem; Pnx2015: Lvds Transmitter; Control Register Interface - Philips 42PF9731D Service Manual

Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.9

PNX2015: Columbus (Comb Filter)

9.9.1 Introduction
This block provides the following picture improvement
functions:
• Enhanced 2D combing for PAL and NTSC.
• 3D field combing for PAL and NTSC.
• 3D frame combing for PAL and NTSC.
• Spatial noise reduction for all component video standards.
• Temporal noise reduction for all component video
standards.
The comb filter is controlled via a separate I
PNX2015, this is to ensure registers containing measurement
information, are accessed at appropriate times. The
measurement information is also available as ancillary data
within the video stream (ITU-656).
For certain features of the comb filter, access to external
memory is required. The PNX2015 has a unified memory that
both comb filter and HD subsystem's share concurrently.
9.9.2 Block Diagram
656
Test
Generator
Pattern
Test
Generator
Y/CVBS
WEA/DAVA
UV
SEL656
Figure 9-25 COLUMBUS internal block diagram
Figure above, shows a block diagram of the Columbus comb
filter in the PNX2015 device. An input video signal is supplied
by the AVIP and fed to the Columbus block. The signal is
supplied in digitized components of:
• CVBS or Y.
• Uncombed U.
• Uncombed V.
The CVBS signal is combed, extracting the luminance
components and rejecting the chroma components. The UV
signals are combed, rejecting the left over luminance
components, from a previous filtering (normally band pass
filtered).
The outputs from the 3D comb filter are:
• Combed luminance signal (Y).
• Combed U signal.
• Combed V signal.
The output from the 3D comb filter feeds the SWAN and LORE
noise reduction block, which performs spatial/temporal noise
reduction, for both luminance and chrominance components.

Control Register Interface

The control registers are accessed via I
2
can be written via I C are double buffered. The fast I
interface implemented on the COLUMBUS is a 5V compliant,
400 kHz slave receiver/transmitter. The I
during voltage shorts or opens.
For the system dependent parameters of the 3D-Comb filter,
five register banks are present. Data can be written in one of
2
C interface on the
CONTROL A(11:0) DQ(16:1)
Memory Interface
Noise
Measurement
2
C. Most signals that
2
C
2
C will not be blocked
the banks via I
SYSTEM_SELECT register. The bits [6:4] of the
SYSTEM_SELECT register select, which register bank is used
by Columbus to define the filter settings.
Bank number
0
1
2
3
4
Internal Test Generators
There are two test generators inside the COLUMBUS chip:
• The "656 test generator" generates a 656 compliant stream
and is used for testing the functionality of the 656 encoder
and decoder. The 656 stream can be injected at the front
end or the back end of the chip.
• A second internal test pattern generator enables testing of
the device and attached external memory (if present). The
test pattern generator signal can be inserted at the front
end of the chip (passing through the 3D Comb and noise
reduction system and external memory) or at the back end
of the chip. Test patterns are available for both PAL/
SECAM and NTSC systems.

9.10 PNX2015: HD Subsystem

The HD subsystem performs MPEG video decoding on HD/SD
transport streams. It interfaces with the PNX8550 and video
coprocessor via tunnel interfaces, HD/SD using DV4 and DV5
Y (ITU656)
inputs, and PNX8550 using DV1, DV2 and DV3 outputs. The
SEL656 HD subsystem can also perform horizontal and vertical scaling
of video images, and perform a range of video measurements
WEB/DAVB
UV (ITU656)
on a transport stream.

9.11 PNX2015: LVDS Transmitter

E_14700_083.eps
300505
Low Voltage Differential Signaling (LVDS) is a low-power, low-
noise differential technology for high speed data transmission
over two PWB traces, or a balanced cable. LVDS allows single-
channel data transmission at hundreds, or even up to a
thousand Mbps. Low swing and current-mode driver outputs
create low noise and provide very low power consumption
across frequency ranges.
The LVDS transmitter IP provides a connection interface to
FPDs.
Differences between standard and LVDS signalling:
• Standard single ended signal (TTL):
–
–
–
–
–
• LVDS:
–
–
–
–
LVDS offers superior performance compared to the standard
single ended signal (TTL).
It is even "protocol independent" so it requires no software.
BJ2.4U/BJ2.5U LA
2
C, by programming bits [2:0] of the
System
PAL B, G, H, I, D, K
PAL M
PAL N
NTSC
Bypass
Requires 28 signal lines and more than 14 grounds.
Single ended signals up to 3 V.
Wide flat ribbon cable.
EMI/EMC problems.
Feasible up to VGA/NTSC resolution (limited to 250
Mb/s).
Five low voltage (350 mV) differential pairs: one clock
pair and four data pairs.
Five grounds.
EMI/EMC friendly.
WXGA and HD-1280x720p (up to 1 Gb/s).
9. EN 165