Panasonic DP-1510P Technical Manual page 6

1. System CPU
The System CPU (SH7041) is a 32-bit RISC (Reduced Instruction Set Computer) type of CPU and
DMA Control, Serial Communication Port, Timer Control, Interrupt Control, DRAM Control, and I/O Port
are integrated into 1 chip. Mask ROM (64k byte) is already installed and it controls the Monitor, High
Speed managing Task and Boot Programming.
• Serial Communication Port
It has a 2ch Serial Communication Port and is used to interface the following devices.
CPU ←→ Panel Unit (Panel CPU)
CPU ←→ Sub CPU for scanning (M16C/162)
• Timer Control
It is used to program the standard timer.
• Interrupt Control
It controls receipt & transfer to CPU the interrupt from MSC, Option, etc.
• DRAM Control
It generates DRAM Control Signal and Refresh Control when the power is ON.
• I/O Port
It is used to control lines and reset control around LSI.
2. System Control Gate Array (MSC)
DZAC000166 (MSC) is a System Control Gate Array and provides the CPU peripheral function.
• DMA Control
It has a 4ch DMA Control and is used to transfer data between the following devices.
Printer Interface ←→ Image Data Memory (DRAM)
• Interrupt Control
It controls receipt & transfer to CPU the interrupt from CODEC and LSI, etc.
• DRAM Control
It selects DRAM Control Signal and generates Control Signal when transferring DMA.
• BUS Control
Data control between System BUS (+3.3V) and I/O BUS (+5V)
• Address Decoder Control
It generates Chip select signal of peripheral LSI.
3. System Memory
This system consists of the following memory.
• F-ROM (IC10) → F-ROM (4MB) for programming
The program is booted from F-ROM Card or Parallel Port Interface.
• DRAM (IC7) → Work RAM
• F-ROM (IC19) → F-ROM (2MB) for image (DP-1810F only).
Edition 1.0
6
DP-1510P/1810P
/1810F/2010E
JUL 2002