Schematic Diagrams - Yamaha PDX-30 Service Manual

A B C

SCHEMATIC DIAGRAMS

MAIN
1
0
0
3.4
2.0
3.4
2.7
2 0
5.0
0
0
0
IC12
0
3.3
0
0
0
0
3.4
3.4
0
0
IC12
0
3
0
0
0 IN L
0
0
0
0
0
0
4
POINT B 1 / Pin 5, 2 / Pin 1 of IC9
POINT A XL1 (Pin 9 of IC10)
5
5 pin 1
1 pin 2
POWER cable ON
6
REGULATOR
JK1
DC IN
15 V
7
8.4
0
0
FET
IC1
8
0
0.7
0
9
10
D E F
IC7
AUDIO PROCESSOR
5 pin 1
1 pin 2
POWER cable OFF POWER cable OFF
REGULATOR
IC6
IC2
0 5.0
IC4
15.4
15.4
IC3 4.5
5.9 3.4
2.5
0 0
0 0
IC12: TC7WH125FK IC11: MFI341S2163
Dual bus buffer IC digital
Vcc H8/300H
G1 1 8 Vcc
Vss MICROPROCESSOR
A1 2 7 G2
System control
Y2 3 6 Y1 Security logic
Internal address bus
GND 4 5 A2
ROM (112 kbytes)
RES RAM (4 kbytes)
Power-on
EEPROM (16 kbytes + 2 kbytes)
reset circuit
Interval timer 1
Interval timer 2
On-chip
Modular multiplication
oscillator
coprocessor
G H
PDX-30
OUT L
15.4 0
3.3 0
1.7
0
1.7
0
IC8
1.7 0
1.7 1.6
DIGITAL
1.7 3.4
0
3.3
AMPLIFIER
0 3.4
No replacement part available.
3.5 2.8
サービス部品供給なし
3.5 3.7
AUTHENTICATION
COPROCESSOR
1.2
3.3
MICRO-
0 3.4
PROCESSOR
0
3.2 3.3
IC10
3.3 0
0 3.4
3.3 0.6
1.9 0
1.4 0
0.8
0
0 A 0
0.2 0
No replacement part available.
サービス部品供給なし
2
1 B
3.4
3.4
0
IC9
0 1.8
IC9: BD5230FVE-TR
Voltage detector IC with adjustable output delay
V DD
P4/IRQ
P3/IRQ 5
I/O port P2/IRQ
P1/IRQ
RNG 1 Vout
WDT
FMU
Voltage monitoring circuit
–
Internal data bus +
20 19 18 17 16
Vref
NC 1 15 NC
2 SUB
2 14
P4/IRQ P3/IRQ
NC 3 Top view 13 P1/IRQ
4 3
RES 4 12 P2/IRQ
GND CT
Vss 5 11 Vss
Register
(512 bytes) 6 7 8 9 10
I J K
IC1:
P-channel silicon MOSFET
Source1
Gate1
Source2
Gate2
CPNTROL (C)
–
CB5
DRIVER L
YE
+
BU
RE
WH +
DRIVER R
–
EXTERNAL
CURRENT LIMIT (X)
LINE-SENSE (L)
FREQUENCY (F)
3.3
3.4
0
No replacement part available.
サービス部品供給なし
IC11
3.4
3.4 3.4
STATUS
indicators
0.6 2.6
CB7 CB6
(for factory) (Writing port)
NCDRC0
IC10: R5F21246SNFP
PVDDREG
Single chip 16 bit microprocessor
8 8 8 6 3 3 8
I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P6
Peripheral functions
A/D converter System clock
(10 bits x 12 channels) generation circuit
Timers
XIN-XOUT
High-speed on-chip oscillator
Timer RA (8 bits) Low-speed on-chip oscillator
Timer RB (8 bits) UART or
XCIN-XCOUT
Timer RD clock synchronous serial I/O
(16 bits x 2 channels) (8 bits x 2 channels)
Timer RE (8 bits)
I 2 C bus interface or clock synchronous
serial I/O with chip select
(8 bits x 1 channel)
LIN module
(1 channel)
Watchdog timer R8C/Tiny Series microprocessor core Memory
(15 bits)
R0H R0L SB ROM (1)
R1H R1L
USP
R2
ISP
R3
RAM (2)
INTB
A0
PC
A1
FLG
FB
NOTES:
Multiplier
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
L M N
PDX-30/PDX-50
IC2: NJM2370U05
ECH8605-TL-E
Voltage regulator
V V
IN OUT
1 8 Drain1
CONT
Thermal
Drain1
2 7 Protection
NOISE
3 6 Drain2 BYPASS
4 5 Drain2
Bandgap
Reference
GND
IC3: DPA424GN-TL
IC power supply
V C
0
Z C INTERNAL DRAIN (D)
1 SUPPLY
SHUNT REGULATOR/
ERROR AMPLIFIER +
SOFT START
- 5.8V -
4.8V
+
5.8V
INTERNAL UV
I FB COMPARATOR
V I(LIMIT) 5.8V
CURRENT
LIMIT SOFT
ADJUST START -
+ 8
ON/OFF
+
V BG +V T
SHUTDOWN
AUTO-RESTART CURRENT LIMIT
COMPARATOR
HYSTERETIC
THERMAL
STOP LOGIC
SHUTDOWN
1V
CONTROLLED
V BG TURN-ON
STOP SOFT- GATE DRIVER
OV/UV START
D MAX
LINE
SENSE DC MAX DC MAX
CLOCK
S Q
-
300/400 kHz SAW LEADING
EDGE
R
+ BLANKING
OSCILLATOR
PWM
COMPARATOR
CYCLE
R E SKIPPING
SOURCE (S)
IC5: NJM431U
Adjustable precision shunt regulator
1 2 3
REFERENCE ANODE CATHODE
IC6: BD9870FPS-E2
High stand voltage 1 channel step-down switching regulator
VCC
1
SW4
VREF
PWM COMP DRIVER
OSC
STBY
5
STBY
CTL
LOGIC OUT
2
TSD OCP
SW5
INV
Error AMP
4
SS
FIN
GND
IC7: LC75348M
Single-chip electronic volume and tone control system
4 3 2 1 30 29 28 27
5 26
LOUT
ROUT
LBASS2 RBASS2
6 25
7 24
LBASS1 RBASS1
8 23
LTRE RTRE
9 22
LIN RIN
21
10
LSELO RSELO
11 12 13 14 15 16 17 18 19 20
IC8: YDA147-SZE2
Digital audio power amplifier
Lch
Feed Back PVDDPL
OUTPL
INLP
Gain Power PWM Level
Logic PVSSL
Control Limit Amp Shift
INLM
OUTML
MUTE
Feed Back
PVDDML
PLIMIT
GAIN0
GAIN1
SLEEPN
MUTEN
CKIN CKOUT
SLEEPN
NCDRC1
Non-Clip MUTEN
Oscillator OTP
3.3V DRC MUTE
OCP
AVDD Regulator Control Control
UVLO
VREF/
VREF PROTN
REF
NC 1 36 NC
NC 2 35 NC
PVDDREG 3 34 GAIN1
AVDD 4 33 GAIN0
INLP 5 32 NCDRC1
Feed Back PVDDPR
MUTE INLM 6 31 NCDRC0
7 30
VREF CKIN
OUTPR 8 29
INRM CKOUT
INRP 9 28
Gain Power PWM Level INRP MUTEN
Logic PVSSR 10 27
Control Limit Amp Shift AVSS PROTN
INRM PLIMIT 11 26
SLEEPN
OUTMR NC 12 25 NC
Feed Back PVDDMR
Rch
★ All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★ Components having special characteristics are marked
and must be replaced
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
● 電圧は、内部抵抗 10MΩの電圧計で測定したものです。
● 印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、
パーツリストに記載されている部品を使用してください。
● 本回路図は標準回路図です。改良のため予告なく変更することがございます。
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