Aiwa XP-SP910 Service Manual page 15

Pin No. Pin Name
49 AVSS1
50 OUTR
51 AVDD1
52 FSEL
53 TMOD1
54 TMOD2
55 FLAG
56 CLVS/IPFLAG
57 EXT0
58 EXT1
59 EXT2
60 TX
61 MCLK
62 MDATA
63 MLD
64 BLKCK
65 SQCK/BCLK
66 SUBQ/LRCK
67 DMUTE/SRDATA
68 STAT
69 NRST
70 SPPOL
71 PMCK
72 SMCK
73 SUBC/SSYNC
74 SBCK/64FS
75 NCLDCK
76 NTEST
77 X1
78 X2
79 DVDD1
80 DVSS1
I/O
— Ground of analog circuits (audio output circuit)
O Rch audio output
— Ground of analog circuits (audio output circuit)
I Noise filter on/off switching input. L: ON; H: OGG
I Terminal mode switching input 1. Normal: L
I Terminal mode switching input 2. Normal: L
O Flag signal output
Command switching.
O • Spindle servo phase sync signal output. H: CLV; L: Rough servo
• Interpolation flag signal output. H: Interpolation
Command switching
I/O
Command switching
I/O
Command switching
I/O
O Digital audio interface output signal
I Microprocessor command clock signal input (latches data at the leading edge).
I Microprocessor command data signal input
I Microprocessor command load signal input. L: Load
Subcode block clock signal: fBLKCK = 75 Hz (during normal playback) / CDTEXT
O
SYNC signal (DQSY): fDQSY = 300 Hz (during normal playback)
Command switching
I/O
Command switching
O • Subcode Q data output
• L/R identification signal output. H: Lch audio data; L: Rch audio data
Command switching
I/O
Status signals (CRC, RESY, CLVS, NTTSTOP, SQOK, FLAG6, SENSE, NFLOCK,
O
NTLOCK, BSSEL, SUBQ data, CDTEXT data, anti-shock read-out data)
I Reset input. L: Reset
O Spindle motor drive signal output (polarity output)
O 88.2 kHz clock signal output
O 4.2336 MHz clock signal output
Command switching
O
Command switching
I
O Subcode frame clock signal output (fCLDCK = 7.35 kHz)
I Test terminal. Normally, H.
I Crystal oscillator input. f = 16.9344 MHz
O Crystal oscillator output. f = 16.9344 MHz
— Power supply of digital circuits
— Ground of digital circuits
19
Description
• Expansion input/output port 0
• SRDATA input
• Expansion input/output port 1
• LRCK input. H: Lch audio data; L: Rch audio data
• Expansion input/output port 2
• BCLK input
• External clock input for Subcode Q register
• Bit clock output for SRDATA
• Muting input. H: Muting
• Serial data output
• Subcode serial outputo
• Sector sync output
• Clock input for subcode serial outputo
• 64FS output