Huawei Y300 Maintenance Manual page 44

Y300 Maintenance Manual
Figure 9-14 Circuit diagram of the 32.768 kHz clock
Analysis
Figure 9-15 shows the block diagram of the 19.2 MHz clock.
Figure 9-15 Block diagram of the 19.2 MHz clock
As shown in Figure 9-15, the 19.2 MHz clock delivers clock signals to the PM8029 and
RTR6285A. The TPK_LO_ADJ controls the clock output precision. The TPK_LO_ADJ has
two levels of filtering circuits: from the R204 to the C232 and from the R3101 to the C3101.
The TPK_LO_ADJ delivers clock signals to the PM8029 and then to the main chip as the
system main clock.
The 32.768 kHz oscillator delivers signals to the PM8029, which provides signals to the
system.
Troubleshooting
Fault symptom: The Y300 fails to be powered on or frequently breaks down. Checks on the
32.768 kHz oscillator show that the X301 and U3101 have no output or the frequencies are
unstable.
Issue 1.0 (2013-01-24) Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
9 Principles and Failure Analysis
39