Level 2 Circuit Board And Standard Parts Replacement; Block Diagram - BenQ BQ060B00 Service Manual

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6. Level 2 Circuit Board and Standard Parts Replacement

The S3C2416X is developed with ARM926EJ core, 65nm CMOS standard cells and a memory complier.

Its lowpower, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive

applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).

The S3C2416X offers outstanding features with its CPU core, a 16/32-bit ARM926EJ RISC processor

cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.

By providing a complete set of common system peripherals, the S3C2416X minimizes overall system costs

and eliminates the need to configure additional components. The integrated on-chip functions that are

described in this document include:

• Around 400MHz @ 1.3V, 266MHz @ TBDV Core, 1.8V/2.5V/3.0V/3.3V ROM/SRAM, 1.8V/2.5V

mSDR/mDDR/DDR2 SDRAM, 1.8V/2.5V/3.3V external I/O microprocessor with 16KB I/D-Cache/MMU

• External memory controller (mSDR/mDDR/DDR2 SDRAM Control and Chip Select logic)

• LCD controller (up to 256K color) with LCD-dedicated DMA

• 6-ch DMA controllers with external request pins

• 4-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)

• 1-ch High Speed SPls

• 1 IIC bus interfaces (multi-master support)

• 1 IIS Audio CODEC interfaces (24-bit, port 0 supports 5.1ch)

• AC97/PCM CODEC Interface(muxed with I2S)

• 2 High-Speed MMC and SDMMC combo (SD Host 2.0 and MMC protocol 4.2 compatible)

• 2-ch USB Host controller (ver 1.1 Compliant)/1-ch USB Device controller (ver 2.0 Compliant)

• 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer

• 10-ch 12-bit ADC and Touch screen interface

• RTC with calendar function

• 138 General Purpose I/O ports / 16-ch external interrupt source

• Power control: Normal, Idle, Stop, Deep Stop and Sleep mode

• On-chip clock generator with PLL

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