Integra DTR-6.8 Service Manual page 77

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -40
Q8001: FLI8125-LF-BC (Video Processor)
BLOCK DIAGRAM
24-bit
Input Port
. .
CVBS
Inputs
S-Video . .
Analog Front
Inputs
End
. .
YPrPb/RGB
Inputs
Sync Stripper
Input
Format
Measurement
Low
Low
. .
Bandwidth
Bandwidth
. .
Analog
ADC
Inputs
IR
IR Sensor
Interface
Input
FEATURES
I
N T E G R AT E D
RGB / YPbPr support up to 135MHz
SCART – RGB + Fast Blank support
Interlaced and progressive scan
External OSD support
D I
I G I T AL N P U T
24-bit re-configurable input port
I
N T E G R AT E D
Worldwide NTSC/PAL/SECAM support
Macrovision / VCR trick mode support
E
M B E D D E D
Turbo 186 core
Internal RAM / ROM
Serial Flash / Parallel ROM support
2-wire slave controller, UART / JTAG support
Internal RESET Controller
GPIOs , Low Bandwidth ADC – 6 input
Infra-red Interface
S E
C AL I N G
Independent H & V scaling factors
4:2:2 YPbPr or 4:4:4 RGB scaling
Anamorphic scaling (non-linear)
Video
Decoder
VBI Slicer
Sync
Processing
Embedded
Micro-processor
Internal Micro-
processor Bus
T ADC F
R I P L E
P
O R T
D
2D V D
I D E O E C O D E R
M
I C R O P R O C E S S O R
OSD C
VBI S
N G I N E
J
Pattern
Generator
Image Processing
ROM
Interface
External ROM
DCD – E ™
AR O U D J A I D G E
Edge Correction
–
Eliminates objectionable stair casing
–
Enhances clarity and realism
Horizontal Enhancement
Adaptive Contrast and Color
Active Color Management
O
I G I T AL U T P U T
18/24-bit 85Mhz TTL output
Dual LVDS up to SXGA
Energy Spectrum Management for reducing
EMI
Programmable CLUT for gamma correction
O N T R O L L E R
Up to 4 windows: 1, 2 or 4-bits per pixel color
Programmable Font scalar to meet Teletext
requirements.
L I C E R
V-Chip, Closed Captioning, XDS, CGMS,
WSS decode
Teletext 1.5 support
S
T AG U P P O R T
Boundary Scan support
OSD
Controller
24-bit RGB /
18-bit RGB /
Output
16-bit YUV
Formatter
TTL Output
DUAL LVDS
DDC2bi
RAM
Interface
Interface
2-wire
Controller
GPIOs
DTR-6.8
GP
Input
/Out-
puts