Sony DVP-NW50 Service Manual page 58

DVP-NW50
Pin No. Pin Name
98 AXR0[10]
99 AXR0[9]
100 AXR0[8]
101 CVDD
102 ACLKX1
103 DVDD
104 CVDD
105 AMUTE1
106 VSS
107 AFSX1
108 GP0[0]
109 VSS
110 AHCLKX1
111 GP0[8]
112 AHCLKR1
113 GP0[3]
114 CVDD
115 VSS
116 GP0[9]
117 GP0[10]
118 GP0[11]
119 GP0[12]
120 CVDD
121 GP0[13]
122 GP0[14]
123 GP0[15]
124 DVDD
125 RESET
126 VSS
127 CVDD
128 CVDD
129 EMU1
130 EMU0
131 TDO
132 DVDD
133 TDI
134 TMS
135 TCK
136 VSS
137 CVDD
138 TRST
139 RSV
140 VSS
141 CVDD
142 PLLHV
143 RSV
144 CLKIN
58
I/O
I/O McASP0 TX/RX data (not used)
I/O McASP0 TX/RX data (not used)
I/O McASP0 TX/RX data (not used)
— Power supply +1.25V
O SCLK signal output
— Power supply +3.3V
— Power supply +1.25V
I Mute control signal input
— Ground terminal
O LRCLK signal output
— Not used
— Ground terminal
I MCLK signal input
— Not used
O MCASP1 receive high-frequency master clock (not used)
— Not used
— Power supply +1.25V
— Ground terminal
— Not used
— Not used
— Not used
— Not used
— Power supply +1.25V
— Not used
— Not used
— Not used
— Power supply +3.3V
I Reset signal input
— Ground terminal
— Power supply +1.25V
— Power supply +1.25V
I/O Select the device functional mode of operation (not used)
I/O Select the device functional mode of operation (not used)
I/O JTAG test-port data out (not used)
— Power supply +3.3V
I JTAG test-port data in (not used)
I JTAG test-port mode select (not used)
I JTAG test-port clock (not used)
— Ground terminal
— Power supply +1.25V
I JTAG test-port reset.
— Not used
— Ground terminal
— Power supply +1.25V
— Power supply +3.3V
— Ground terminal
I Clock input
Description