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6-5. BLOCK DIAGRAM — AMP SECTION —
X301
24.576MHz
MCLK
LRCK
SCLK
SDATA
MAIN(1)
C
SECTION
(Page 24)
RXD_ARM
TXD_ARM
MAIN(2)
DIMMNG_CON
D
SECTION
(Page 25)
U202
SPI SERIAL
X201
MEMORY
7.3728MHz
1
CS
6
SCK
5
SI
2
SO
• SIGNAL PATH
: AUDIO(ANALOG)
: AUDIO(DIGITAL)
DVP-NW50
144 CLKIN
107
AFSX1
102
ACLKX1
97
AXR0(11)
U301
95
AXR0(12)
DIGITAL SIGNAL
94
AXR0(13)
PROCESSOR
110 AHCLKX1
92
AXR0(14)
88 AFSR1
110
AHCLKX1
89 ACLKR1
91 AXR0(15)
9 PD0(RXD)
10 PD1(TXD)
RESET
4
16 PD7(OC2)
7 XTAL2
U201
MICRO
19
PCO(SCL)
8 XTAL1
CONTROLLER
20
PC1(SDA)
37 PA0(ADC0)
14
PD5(OC1A)
36 PA1(ADC1)
35 PA2(ADC2)
42
PB2(AIN0/INT2)
34 PA3(ADC3)
PD3(INT1)
12
PC2(TMS)
21
U401
DIGITAL AUDIO
PROCESSOR
26 LRCLK
27 SCLK
28 SDIN4
SDIN3
29
SDIN2
30
SDIN1
31
63 MCLK
PWM_P_1
41
PWM_M_1 40
PWM_P_2
43
14 MUTE
PWM_M_2 42
PWM_P_3
45
PWM_M_3 44
PWM_P_4
47
19 XTL_OUT
PWM_M_4 46
PWM_P_7
50
3.3VCC
X401
20 XTL_IN
PWM_M_7 49
13.5MHz
PWM_P_8
52
PWM_M_8 51
25 SCL
VALID 39
24 SDA
11 RESET
32 PSVC
BKND_ERR 37
1.25V(CVDD)
MAIN(3)
3.3VDC
E
SECTION
14VDC
(Page 26)
27
27
U402
DIGITAL AUDIO AMP
29
OUT_B
2 PWM_BP
LPF
30
25
OUT_A
LPF
17
PWM_AP
26
RESET
4
Q402, 403
13
DC
DETECT
U403
DIGITAL AUDIO AMP
29
OUT_B
2
LPF
PWM_BP
30
17
PWM_AP
OUT_A
25
LPF
26
4 RESET
Q404, 405
13
DC
DETECT
U501
DIGITAL AUDIO AMP
OUT_B
29
2
PWM_BP
LPF
30
OUT_A
25
PWM_AP
LPF
17
26
4 RESET
Q501, 502
13
DC
DETECT
U502
DIGITAL AUDIO AMP
29
OUT_B
2
30
LPF
PWM_BP
25
OUT_A
17
PWM_AP
LPF
26
4 RESET
Q503, 504
13
DC
DETECT
U601
DIGITAL AUDIO AMP
OUT_B
29
2
PWM_BP
LPF
30
OUT_A
25
17
PWM_AP
LPF
26
4 RESET
Q601, 602
13
DC
DETECT
U602
DIGITAL AUDIO AMP
OUT_B
29
2
LPF
30
PWM_BP
OUT_A
25
17
PWM_AP
LPF
26
4 RESET
Q603, 604
13
DETECT
Q401
PROTECT DETECT
U102
+1.25V REG
U101
3.3V(DVDD)
+3.3V REG
VCC3.3V
3.3VCC
29.5V
U103
29.5V
+12V REG
VCC12V
Q101
CURRENT
DETECTOR
DVP-NW50
J401-A
(–)
FRONT
(+)
R
J402-B
(+)
FRONT
L
(–)
SPEAKERS
(IMPEDANCE
USE 8-16Ω)
J501-A
(–)
SUR
(+)
L
J501-B
(+)
SUR
R
(–)
J601-A
(–)
CENTER
(+)
J601-B
(+)
SUB WOOFER
(–)
DC
J103
14V
DC IN
(TO AC-NW50)

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