Sony DVP-NW50 Service Manual page 50

DVP-NW50
Pin No. Pin Name
48 AD0
49 VDD_RING
50 GND_RING
51 NC
52 NC
53 VDD_RING
54 GND_RING
55 AD15
56 DA7
57 VDD_CORE
58 GND_RING
59 AD14
60 DA6
61 AD13
62 DA5
63 AD12
64 DA4
65 AD11
66 VDD_RING
67 GND_RING
68 DA3
69 AD10
70 DA2
71 AD9
72 DA1
73 AD8
74 DA0
75 DSRN
76 DTRN
77 TCK
78 TDI
79 TDO
80 TMS
81 VDD_RING
82 GND_RING
83 BOOT1
84 BOOT0
85 GND_RING
86 NC
87 EECLK
88 EEDAT
89 ASYNC
90 VDD_CORE
91 GND_CORE
92 ASDO
93 SCLK1
94 SFRM1
95 SSPRX1
96 SSPTX1
50
I/O
O Shared address bus out
— Power supply +3.3V
— Ground terminal
— Not used
— Not used
— Power supply +3.3V
— Ground terminal
O Shared address bus out
I/O Shared data bus in/out
— Power supply +1.8V
— Ground terminal
O Shared address bus out
I/O Shared data bus in/out
O Shared address bus out
I/O Shared data bus in/out
O Shared address bus out
I/O Shared data bus in/out
O Shared address bus out
— Power supply +3.3V
— Ground terminal
I/O Shared data bus in/out
O Shared address bus out
I/O Shared data bus in/out
O Shared address bus out
I/O Shared data bus in/out
O Shared address bus out
I/O Shared data bus in/out
O Data set ready/data carrier detect (not used)
O Data terminal ready out
I JTAG clock in
I JTAG data in
O JTAG data out
I JTAG test mode select
— Power supply +3.3V
— Ground terminal
I Boot mode select in (not used)
I Boot mode select in (not used)
— Ground terminal
— Not used
O Two-wire interface clock output
O Two-wire interface data output
I Frame clock LRCK input
— Power supply +1.8V
— Ground terminal
O Transmit data output
I/O SPI bit clock (not used)
I/O SPI frame (not used)
I/O SPI input (not used)
I/O SPI output (not used)
Description