Table of Contents
Advertisement
Circuit Description
Frequency Synthesizer Circuit
The PLL(Phased Locked Loop) block consists of VC-TCXO(OSC302), PLL in S1M8690X and
VCO(OSC301). Input reference frequency is generated at VC-TCXO(OSC302) and the RF
local signal is generated at VCO. PLL compares the two signals and generates the desired
signal with a preprogrammed counter which controls voltage.
VC-TCXO
The VC-TCXO (OSC302) is a reference source of the frequency synthesizer. It provides 19.2MHz
reference frequency to PLL-IC. It is a voltage controlled temperature compensated crystal
oscillator having 19.2MHz ±2.5ppm frequency stability over all useful temperature range.
A correct frequency tuning is made by the control voltage.
2-3-2. Transmitter
Intenna
Intenna sends signal to the base station and receives the signal from the base station.
It is a tri-band Intenna and covers PCS band, CDMA band and GPS band.
RF Switch
It(U405) is used to switch the PCS path, the CDMA path and the GPS path, The RF signal
passes through PCS & CDMA path when GPS_MODE is low.
GPS_MODE is a digital signal from MSM6500 GPIO.
Duplexer
Duplexer(F405) passes the RF signal of Rx frequency range(881.49 ±12.5 MHz) and Tx frequency range
(836.49 ±12.5 MHz). It provides appropriate attenuation of transmitted signal at the receiver input and
appropriate rejection of the transmit-generated noise in the Receiver band.
It also matches LNA input in receiving part and PAM(U403:ACPM-7813) output in transmitting part with
the Intenna.
2-8
SAMSUNG Proprietary-Contents may change without notice
This Document can not be used without Samsung's authorization
Advertisement
Table of Contents
