Table of Contents
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* PIN DESCRIPTON
Name
VCC
LA[21:0]
8, 17, 26, 34, 43, 52, 60, 67, 76, 84, 91, 98, 103,
VSS
147,156,163,171,177,184, 192, 200, 208
RESET#
TDMDX
RSEL
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS
SEL_PLL1
TSD
SEL_PLL0
SEL_PLL2
MCLK
TBCK
SDIF_DOBM
RSD
RWS
RBCK
APLLCAP
XIN
XOUT
DMA[11:0]
DCAS#
DOE#
DSCK-EN
DWE#
DRAS[2.0]#
DB[15:0]
DCS[1:0]#
DQM
DSCK
DCLK
YUV[7.0]
PCLK2XSC
N
PCLKQSCN
VSYNCH#
HSYNCH#
Number
1, 9, 18, 27, 35, 44, 51, 59, 68, 75, 83,
92, 99, 104, 111,
121, 130, 139, 148, 157, 164, 172, 183,
193, 201
23:19, 16:10, 7:2, 207:204
112, 120, 129, 138,
24
25
28
29
30
31
32
33
36
39
40
41
45
46
47
48
49
50
66:61, 58:53
69
70
71
74:72
96:93, 90:85, 82:77
97,100
101
102
105
115:113, 110:106
116
117
118
119
I/O
Definition
I
3.65 V ± 150 mv.
O
Device address output
I
I
Reset input active low.
O
TDM transmit data
ROM Select
RSEL
I
0
1
I
TDM receive data.
I
TDM clock input.
I
TDM frame synch.
O
TDM output enable, active low.
O
Audio transmit frame sync.
I
Select PLL1.
Audio transmit serial data port.
Select PLL0.
SEL_PLL2 SEL_PLL0 Clock Output
O
0
I
0
1
1
Select PLL2. See the table for pin number
I/O
Audio master clock for audio DAC.
I/O
Audio transmit bit clock.
O
S/PDIF (IEC958) Format Output.
I
Audio receive serial data.
I
Audio receive frame synch.
I
Audio receive bit clock.
I
Analog PLL Capacitor.
I
Crystal input.
O
Crystal output.
O
DRAM address bus.
O
Column address strobe, active low.
O
Output enable, active low.
I
Clock enable, active low.
O
DRAM write enable, active low.
O
Row address strobe, active low.
I/O
DRAM data bus.
O
SDRAM chip select [1:0], active low.
O
Data input/ output mask.
O
Clock to SDRAM.
I
Clock input (27MHz).
O
8-bit YUV output.
I/O
2X pixel clock.
I/O
Vertical synch for screen video interface,
I/O
programmable for rising or falling edge,
Horizontal synch for screen video interface,
I/O
programmable for rising or falling edge,
Ground
Selection
16-bit ROM
8-bit ROM
0
2.5 x DCLK
1
3 x DCLK
0
3.5 x DCLK
1
4 x DCLK
33.
Pixel clock.
active low.
13
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