Circuit Description - Kenwood DVF-3060 Service Manual

DVF-3060/3060-S/3060K-S
1. Port list sorted by function for MPEG Processor IC(Main IC21)
Port No.
Audio DAC
51 DAC SCLK (BCK)
52 DAC PCMOUT0
53 DAC PCMOUT1
54 DAC PCMOUT2
55 DAC PCMCLK
56 DAC LRCLK
57 SPDIF OUT
48 VDD PCM
49 VSS PCM
Clock & Reset
124 RESET
122 VDD PLL
123 VSS PLL
120 PIX CLK
PIOs and communication
186 PIO0(0) T STROBE
187 PIO0(1) MOD SW
188 PIO0(2) VFD STB
189 PIO0(3) VFD CLK
190 PIO0(4) VFD DATA OUT
191 PIO0(5) VFD DATA IN
PIO0(6) SLIDER SENSOR
192
OPEN/CLOSE (DRAWER POSITION)
PIO0(7) SLIDER IN
193
(DRAWER CCW/CTRL)
194 PIO1(0) SDA
195 PIO1(1) SCL
PIO1(2) SLIDER OUT
196
(DRAWER CW CTRL)
197 PIO1(3) TXD(JIG)
200 PIO1(4) RXD(JIG)
201 PIO1(5) FRONT TXDI
202 TRIGGER IN
203 TRIGGER OUT
204 PIO2(0) H/P IND
205 PIO2(1) FRONT RXD
✽
206 PIO2(2) MIC DET
207 PIO2(3) MIC MUTE
208 PIO2(4) AUDIO MUTE
1 PIO2(5) RGB SEL(BLANK)
2 PIO2(6) VIDEO MUTE
3 PIO2(7) 16: 9 INDICATOR
6 PIO3(0) SCART H (TV/AUX)
7 PIO3(1)
✽
8 PIO3(2) CSB
✽
9 PIO3(3) SDIN
10 PIO3(4) IR REMOCON
✽
11 PIO3(5) SCLK
12 PIO3(6)
13 PIO3(7) DVD RESET
39 PIO4(0)HP MUTE
40 PIO4(1)
41 PIO4(2) DAC SCKDSD
4

CIRCUIT DESCRIPTION

Port Name I/O
O
O
O
O
O
O
O
-
-
-
-
I/O Flash ROM down-load JIG module signal.
I/O Flash ROM down-load JIG module signal.
O
O
O
I/O Detection port of slider sensor for DVD mechanism.
I/O Control port of slider (IN) for DVD mechanism.
I/O 12C serial data.
I/O 12C serial clock.
I/O Control port of slider (OUT) for DVD mechanism.
I/O UART TXD
I/O UART RXD
I/O Unused.
I/O Trigger input from JIG.
I/O Trigger output from JIG.
-
-
-
O
I/O RGB sel (blank).
I/O Video mute control.
I/O 16 : 9 indicator (E/T type only)
I/O Unused.
I/O Unused.
O
O
I/O IR Remote controller signal output.
O
I/O Unused
I/O Power- on reset of front-end module.
-
-
O
Port Description
DAC sampling clock.
DAC PCM data out 0.
DAC PCM out 1 (unused).
DAC PCM out 2 (unused).
DAC PCM clock.
DAC PCM Left/Right clock.
Audio digital data output.
Supply voltage for PCM (+2V5).
Ground for PCM.
I Chip reset input.
Supply voltage for PLL (+2V5).
Ground for PLL.
I 27MHz main clock input.
VFD strobe output.
VFD clock output.
VFD data output.
I Data input from VFD.
Unused.
Unused.
I Detection port of MIC jack.
Unused.
Audio mute control.
3-wire MPU chip select/2-wire MPU interface address selection.
3-wire MPU data output /2-wire MPU data output.
3-wire MPU clock output /2-wire MPU clock output.
Unused.
Unused.
DAC system clock output
E/T type only