Yamaha KMA-1080 Service Manual page 17

No. Pin Name Function Name Type I/O Description of Function
87 Vss VSS
88 STBY STBY IO I Standby input
89 PG0/CS0 PG0 IO O
90 PG1/CS1 DSP6_CS CS1 O DSP6 interface
91 PG2/CS2/RAS2* PG2 IO O
92 PG3/CS3/RAS3* PG3 IO O
93 AVcc AVCC
94 Vref VREF
P40/IRQ0-B/
95 P40 IO O AD-0
AN0_0
P41/IRQ1-B/
96 P41 IO O AD-1
AN1_0
P42/IRQ2-B/
97 P42 IO O AD-2
AN2_0
P43/IRQ3-B/
98 P43 IO O AD-3
AN3_0
P44/IRQ4-B/
99 DSP6_INT INT I DSP6 interface
AN4_0
P45/IRQ5-B/
100 DSP6_LEVEL IO I DSP6 interface
AN5_0
P46/IRQ6-B/ Howling reduction mode
101 HR_CTRL1 IO I
AN6_0 detection １
102 P47/IRQ7-B/ Howling reduction mode
HR_CTRL2 IO I
AN7_0 detection 2
103 P94/AN12_1/DA2 P94 IO O DA-2
104 P95/AN13_1/DA3 DIAG_IN IO I Input for PCB inspection
105 AVss AVSS
PG4/BREQO-A/
106 E10A_PG4 IO I Interface for E10A
CS4
107 PG5/BACK-A E10A_PG5 IO I Interface for E10A
108 PG6/BREQ-A E10A_PG6 IO I Interface for E10A
P50/BREQO-B/
IRQ0-A/PO0-B/
109 TIOCA3-B/ P50 IO O
TMRI0-B/TxD2/
SDA3
P51/BREQ-B/
IRQ1-A/PO2-B/
110 TIOCC3-B/ P51 IO O
TMCI0-B/RxD2/
SCL3
P52/BACK-B/
IRQ2-A/PO4-B/
111 P52 IO O
TIOCA4-B/
TMO0-B/SCK2
112 P53/IRQ3-A/
E10A_P53 IO I Interface for E10A
ADTRG0-A
P35/OE-B*/SCK1/
113 ISP_SCK1 IO O Writer (for ISP-310)
SCL0
114 P34/SCK0/
P34 IO O
SCK4-A/SDA0
115 P33/RxD1/SCL1 ISP_RXD1 IO O Writer (for ISP-310)
P32/RxD0/IrRxD/ For inspection of DSP PCB
116 P32 IO I
SDA1 （loop back）
117 P31/TxD1 ISP_TXD1 IO O Writer (for ISP-310)
For inspection of DSP PCB
118 P30/TxD0/IrTxD P30 IO O
（loop back）
119 MD0 MD0 IO I MCU operation mode setting
120 MD1 MD1 IO I MCU operation mode setting
※ 1: Do not connect to the power source but connect to Vss via 0.1µF (recommended value) capacitor. (Position near the terminal.)
Hardware Software
terminal terminal Remarks
treatment treatment
GND
H -
GND L Free １
CS H -
GND L Free １
GND L Free １
VCC
VCC
GND L Free ２ (for input only)
GND L Free ２ (for input only)
GND L Free ２ (for input only)
GND L Free ２( (for input only)
INT H
Level fl ag L PORT
H -
H -
GND L Free ２
In normal state：Low / For
L -
inspection：High
GND
In normal state：Low / When
L -
E10A connected：High
In normal state：Low / When
L -
E10A connected：High
In normal state：Low / When
L -
E10A connected：High
GND L Free １
GND L Free １
GND L Free １
In normal state：Low / When
L -
E10A connected：High
H H
GND L Free １
H H
In normal state：Low / For
L -
inspection：High
H H
Inspection result ＯＫ：High、
- L
ＮＧ：Low
H - Mode ７
H - Mode ７
IC17: YSS910C-VZ (DSP P.C.B.)
DSP6 (Digital Signal Processor)
* No replacement part available.
NC 133 88
VDD5 134 87
DA16 135 86
DA17 136 85
DA18 137 84
DA19 138 83
DA20
139 82
DA21 140 81
DA22 141 80
DA23 142 79
VSS 143 78
DA24
144 77
DA25 145 76
DA26 146 75
DA27
147 74
DA28 148 73
DA29
149 72
DA30 150 71
DA31
151 70
VDD5
152 69
VSS 153 68
A00
154 67
A01 155 66
A02
156 65
A03
157 64
A04 158 63
A05
159 62
A06
160 61
A07
161 60
A08
162 59
A09 163 58
VSS
164 57
VDD
165 56
A10
166 55
A11
167 54
A12
168 53
A13
169 52
A14
170 51
A15/RAS
171 50
A16/CAS
172 49
A17/CE
173 48
/WE
174 47
/OE
175 46
VDD5
176 45
Port Name I/O
XI I System master clock input (60MHz or 30MHz)
XO O System master clock output (60MHz or 30MHz)
/SYNCI I System synchronous signal input
CKI I System clock input (30MHz)
/SYNCO O System synchronous signal output
CKO O System clock output (30MHz)
CKSEL I System master clock select (0:60MHz, 1: 30MHz)
MCKS I Master clock input for serial I/O (128 x Fs)
/SSYNC I Synchronous signal input for serial I/O
/IC Is Initial clear
/TEST I+ Test mode setting (0: Test, 1: Normal)
CD14-00 I/O Host CPU data bus
CA0/CD15 I/O Host CPU address bus / data bus
CA7-1 I Host CPU address bus
BTYP I Host CPU data bus width select (0: 8 bit, 1: 16 bit)
/CS Is+ Chip select signal input
/RD Is+ Read signal input
/WR Is+ Write signal input
/IRQ O IRQ output
TRIG I/O Transfer trigger signal input/output
/WAIT O WAIT output
SI7-0 I+ Serial data input
SO7-0 O Serial data output
DB31-00 I+/O Parallel data bus
TIMO/DBOE I/O Timing signal output / parallel data bus output control input
DA31-00 I+/O External memory data bus
A17/CE O External memory address (SRAM), /CE (PSRAM)
A16/CAS O External memory address (SRAM, PSRAM), /CAS (DRAM)
A15/RAS O External memory address (SRAM, PSRAM), /RAS (DRAM)
A14-12 O External memory address (SRAM, PSRAM)
A11-00 O External memory address (SRAM, PSRAM, DRAM)
/WE O External memory Write Enable signal
/OE O External memory Output Enable signal
(N.C.) – No connection
VDD5 – +5V
VDD – +3.3V
VSS – Ground
KMA-1080/KMA-980
VDD CPU CLOCK
VDD5
INTERFACE GENERATOR
DB12
DB11
DB10
DB09
DB08
DB07
CTL-BUS
DB06
DB05
DB04
DB03
DB02
32
DB01
DA31~00
DB00 320 STEP
VSS
DSP 18
SO7
I/O BUS 320 STEP A17~00
EXTERNAL
SO6
SO5 CONTROL DEQ
320CH RAM
SO4
/WE
INTERPOLATER INTERFACE
SO3
SO2
SO1
/OE
SO0
VDD5
VSS
SI7 I/O-BUS
SI6
SI5
SI4
SI3
SI2
SI1
SI0 SERIAL SERIAL
VSS
INPUT OUTPUT PARALLEL MOD
/WAIT FUNCTION
CD00 32CH INPUT 32CH OUTPUT IN/OUT 8 BIT/16CH
CD01
BUFFER BUFFER
CD02
CD03
CD04
CD05
VDD5
VDD
Function
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