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Principles
of Operation
The
rising
edge
of
SENSEPULSE
clocks a high
into flip-flop
U24
(74HCT74).
This
converts
the signal into
a
level that
can be
read
by
the
microprocessor through
the
PB7
input
of
U9
(6522A VIA)
as signal
LPSENSE
(low
true).
If
the
low
true
SLAVE
signal
from
U
lO
(65C21 PIA)
is
high
(i.e.,
the unit
is
either a
stand-alone or master),
the
micro-
processor reads
its
own U24
flip-flop.
The
output of
U24
also
gets driven
onto
the
LPSENSE
line
of
the
master/slave
con-
nectors.
If
SLAVE
is
asserted, the
microprocessor
reads the
LPSENSE
signal
from
the
master/slave connectors.
The
microprocessor can
clear
flip-flop
U24
by
setting
the
LPRESET
output
of
U9
high.
This
signal also gets
driven
onto
the master/slave
connectors
by
open-collector driver
Lf21.
This
method
permits
the
master and
all
slaves
in
a
mas-
ter/slave
system
to
read
and
clear the
U24
flip-flop in
the
master
unit.
Thus,
one
light
pen
can
serve
for
all
units,
while
each
unit controls
its
own
display
for
the
scan
routine.
The
switch
signal
(low
true
LPS
WITCH)
goes
to the
CAl
interrupt input
of
the
VIA, which
is
programmed
to
generate
an
IRQ
interrupt
on
the
falling
edge of
LPSWITCH.
The
interrupt service
routine stops the
normal
display refresh
multiplexing
and
takes
over
control
of
the display.
The
routine
then scans the display
one column
at
a time,
clearing
flip-flop
U24
before scanning
each column.
After
the
display
is
scanned,
the
processor
examines
the
LPSENSE
signal to
determine
if
the
light
pen
"sees"
one of
the
LEDs
that
is
currently
being scanned.
If
a
master scans
its
display
and
gets
no
response
from
the
light
pen,
it
instructs the
slaves
in
turn to
scan
their
displays.
Each
slave
monitors
the
U24
flip-flop
of
the
master
to
check
whether
or not the
light
pen
"sees"
any of
the
LEDs
that
are
lit
on
its
own
display.
6.7
Master/slave
circuitry
The
master/slave
interface
is
a
closed loop of
serial
commu-
nication
and bused
control
signals.
Its
control
circuitry
resides
on
the
digital
board.
See
Figure
6-1
1
for
a
simplified
schematic.
Each mainframe
has
a
Master/Siave
In
connector
and
a
Mas-
ter/Siave
Out
connector.
Serial
data
is
sent
from
the
TXDATA
pin
of
the
output connector
to
the
RXDATA
pin
of
the input
connector
on
the
next
mainframe
in
the loop. All
other
interface
signals
(M/S
TRIGGER, ALLREADY,
LPRESET,
and
LPSENSE)
are
common
to
input
and
output
connectors.
The
light
pen
signals
LPRESET
and
LPSENSE
are
described
in
paragraph
6.6.
6.7.1
Serial
communication
Serial
data
communication
is
managed
by
Ull
(68B50
ACIA)
and automatic
retransmit
logic:
a
U22
NAND
gate
used
as
an
inverter,
U5
AND
gates,
and
U18
OR
gate.
The
RTS
(low
true)
output of
U1
1
controls the
automatic
retransmission of
serial
data.
Stand-alone
and
master
units
assert
RTS
to
gate the
TXDATA
output of
U1
1
through a
U5
AND
gate
and
via
U1
8 onto the
TXDATA
pin
of the master/
slave
interface.
Relay
K1
is
energized
(as
shown) whenever
power
is
applied
to
the
Model
707
A.
Slave
units
negate
RTS
except
when
responding
to
a request
by
the
master
for
setup or
status
information.
A
negated
RTS
signal
blocks
the
TXDATA
signal
at
its
corresponding
U5
AND
gate.
Incoming
serial
data
to
the
RXDATA
input
of
Ull
is
also
routed through a
U5
gate,
the
U18
OR
gate,
and
onto
the
master/slave
TXDATA
pin
to effect
the
automatic
retransmission.
6-15
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