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6
Principles
of
Operation
6.1
INTRODUCTION
This
section contains a functional description
of
the
Model
707
A
in
block diagram
form
as well as details
of
the various
sections
of
the
instrument.
Information
is
arranged
to
provide a
description
of each of
the functional
blocks within
the
instrument.
Many
of
these
descriptions
include
simplified
schematics
and
block diagrams.
Component
layout
drawings
are located
at
the
end
of Section
8.
6.2
Overall function description
The Model 707A
mainframe
contains three
circuit
boards,
primarily
digital,
and a
power
supply.
Relay
switching cards
that
plug
into the
mainframe
have analog
circuits for signal
paths
and
digital circuits
for control.
Figure
6-1
shows
the
interconnection of
the
mainframe's
digital
board,
front
panel
display board,
and backplane
in
a
block diagram.
The
following paragraphs describe
Model
707A
circuitry
by
function, with
some
functions residing
on
more
than
one
board
(e.g,,
relay
control
circuits
and
display
circuits).
6.3
Microcomputer
The Model
707
A
is
controlled
by
an
internal
microcomputer.
As shown
in
the
block diagram of Figure
6-2, the
digital
board
contains
the
CPU,
memory, and
associated
compo-
nents:
•
68B09
microprocessor (U6)
•
Oscillator (Yl)
•
Power-up
reset
(U17)
•
Address decoding
PALs
(U
1
,
U2)
•
32Kx8~bit
EPROM
(U7)
•
32Kx8-bit
RAM
(U8) with
battery
back-up (BTl,
U3)
The
microcomputer
centers
around
the 8-bit
68B09
micro-
processor.
The
MPU
has
direct control
over
relay
switching,
front
panel displays
and
switches,
and
rear
panel
interfaces
(master/slave,
digital
I/O,
IEEE-488
bus,
and
triggers).
Although
the
68B09
microprocessor
will
operate
at
frequen-
cies
up
to
8MHz,
a clock frequency
of
7.15909MIiz
is
used
to
reduce
interference
with instruments
that
use
measure-
ment
signals
with harmonics of
IMHz.
Crystal
Yl
provides
timing
for the
microprocessor.
Internally,
the
clock
fre-
quency
is
divided
down
by
four
to
obtain
an
operating
fre-
quency
on
the
microprocessor bus of
1.
78977MHz.
6.3.1
Reset
circuit
The
reset circuit,
which
is
based on
an 821
1
(or
6728)
volt-
age
detector
(U17), senses
the
output of
the
power
supply.
When
the
output drops
below
approximately
4.6V, the
8211
asserts
the
RESET
(low
true)
line.
Two 1%
resistors
(R34
and R35) form
a voltage
divider,
which
is
calibrated
to
match
the
comparator
threshold voltage of the 821
1
by
either
removing
or leaving
in
R36,
which
is
in
parallel
with
R35.
During power-off
or
brownout
conditions, the
RESET
line
must
be asserted before
the
power
supply drops
into the
com-
parator threshold
range
(4.25
to 4.5 volts)
of
the
DS-1210
non-volatile
RAM
controller
(U3).
During power-up, capac-
itor
C91
is
charged up
to
delay
the
RESET
line
going high
for
1
10
to
260msec.
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