Table of Contents
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A
B
C
RX-V675/HTR-6066/TSR-6750
DIGITAL 7/8
1
N O T I C E
( m o d e l )
J
J A P A N
U
U . S . A
C
C A N A D A
R
G E N E R A L
+ 3 . 3 D S P
T
C H I N A
C 9 3 0 3
K
K O R E A
A
A U S T R A L I A
n o _ u s e
C 9 3 0 4
B
B R I T I S H
n o _ u s e
G
E U R O P E
C 9 3 0 5
L
S I N G A P O R E
n o _ u s e
C 9 3 0 6
2
E
S O U T H E U R O P E
V
T A I W A N
n o _ u s e
C 9 3 0 7
F
R U S S I A N
n o _ u s e
P
L A T I N A M E R I C A
C 9 3 0 8
S
B R A Z I L
n o _ u s e
C 9 3 0 9
H
T H A I
n o _ u s e
C 9 3 1 0
n o _ u s e
RESISTOR
REMARKS
PARTS
NAME
NO MARK
CARBON
FILM
RESISTOR
(P=5)
CARBON
FILM
RESISTOR
(P=10)
METAL
OXIDE
FILM
RESISTOR
METAL
FILM
RESISTOR
METAL
PLATE
RESISTOR
FIRE
PROOF
CARBON
FILM
RESISTOR
CEMENT
MOLDED
RESISTOR
SEMI
VARIABLE
RESISTOR
3
CHIP
RESISTOR
CAPACITOR
REMARKS
PARTS
NAME
NO
MARK
ELECTROLYTIC
CAPACITOR
TANTALUM
CAPACITOR
NO
MARK
CERAMIC
CAPACITOR
CERAMIC
TUBULAR
CAPACITOR
POLYESTER
FILM
CAPACITOR
POLYSTYRENE
FILM
CAPACITOR
MICA
CAPACITOR
P
POLYPROPYLENE
FILM
CAPACITOR
SEMICONDUCTIVE
CERAMIC
CAPACITOR
POLYPHENYLENE
SULFIDE
FILM
S
CAPACITOR
4
DIGITAL IN
A V 4 _ D
A V 4 _ D
A V 3 _ D
A V 3 _ D
A V 2 _ D
A V 2 _ D
A V 1 _ D
to DIGITAL 8/8
A V 1 _ D
B T _ S P D I F
B T _ S P D I F
A D _ L
( Z 2 _ A D L )
A D _ L
A D _ R
( Z 2 _ A D R )
A D _ R
ANALOG IN
T P
A
R 9 2 1 5
+ 3 . 3 D R 1
3 3
5
L 9 2 0 4
R 9 2 3 3
B K P 1 0 0 5 H S 6 8 0 - T
n o _ u s e
R 9 2 7 3
D S P _ M I S O
1 0 K
R 9 2 7 4
3 3
D S P _ M O S I
D G N D
D S P _ S C K
M C / S C L
D I R 1 _ N _ C S
R 9 2 2 0
M S / A D R 1
DIR
1 0 0
M O D E
R 9 2 3 6
T P
1 0 0 K X 4
Z A D C _ S D O
A
R X I N 7 / A D I N 0
Z A D C _ W C K
R X I N 6 / A L R C K I 0
Z A D C _ B C K
R X I N 5 / A B C K I 0
Z A D C _ M C K 2
R X I N 4 / A S C K I 0
H D M I _ A U D _ R T N
R X I N 3
D G N D
H D I G _ D S D 0 A
R X I N 2
D I R _ N _ R S T
R 9 2 2 1
R S T
1 0 0
A V 3 _ D
R X I N 1
+ 3 . 3 D R 1
L 9 2 0 5
V D D R X
6
B K P 1 0 0 5 H S 6 8 0 - T
A D _ R
A D _ L
A V 4 _ D
L 9 2 0 3
C 9 2 7 5
B K P 1 0 0 5 H S 6 8 0 - T
X L 9 2 1
1 0 / 6 . 3
4
3
1
2
2 4 . 5 7 6 M H Z
A G N D
( 0 . 5 % ) ( 0 . 5 % )
R 9 2 6 9
R 9 2 7 1
D G N D
1 . 8 K
1 . 8 K
C 9 2 6 9
C 9 2 7 0
7
8 2 0 P / 1 6
8 2 0 P / 1 6
V 6 7 5 - A 8 3 0 : 2 . 4 V r m s t o 3 V p p
R 9 2 6 8 , 9 2 7 2 = 2 . 4 k
R 9 2 6 9 , 9 2 7 1 = 2 . 4 k
8
9
IC922: M12L64164A-5TG
1M x 16-bit x 4 banks synchronous DRAM
CLK
Clock
Generator
CKE
Row
Address
Address
Buffer
Mode
Bank A
and
Register
Refresh
Counter
10
Sense Amplifier
CS
Column
Address
Column Decoder
RAS
Buffer
and
Refresh
CAS
Counter
Data Control Circuit
WE
D
E
F
RX-A730
+ 1 . 2 D S P 1
+ 1 . 2 D S P 1
1.2
+ 1 . 2 D S P 1
I C 9 2 9
+ 3 . 3 D S P
R 1 1 7 2 H 1 2 1 D - T 1 - F
C 9 3 1 2
n o _ u s e
5
4
C 9 3 1 3
X 9 2 9 2 A 0
n o _ u s e
1
2
3
D G N D
V +
V +
5
5
3
3
V -
V -
D G N D
V c e h = 1 ~ 6 V
D G N D
V c e l = 0 - 0 . 4 V
T C 7 S H 3 2 F U
I C 9 2 6
2
R 9 2 9 3
4
1
3 3
D G N D
2
R 9 2 9 4
4
1
3 3
I C 9 2 7
T C 7 S H 3 2 F U
R S V 2
+ 1 . 2 D S P 1
1 3 3
U S B 0 _ V D D A 1 2
1 3 4
U S B 0 _ V D D A 1 8
1 3 5
L 9 2 0 8
N C
1 3 6
C 9 2 9 6
B K P 1 0 0 5 H S 6 8 0 - T
C 9 2 1 6
C 9 2 1 7
U S B 0 _ D P
1 0 0 0 P ( B )
1 3 7
0 . 1 / 1 0 ( B J )
0 . 0 1 / 1 6 ( B )
U S B 0 _ D M
L 9 2 0 9
1 3 8
N C
B K P 1 0 0 5 H S 6 8 0 - T
1 3 9
U S B 0 _ V D D A 3 3
C 9 2 1 4
X L 9 2 2
1 4 0
Z A D C _ M C K 1
1 8 P ( C H )
2 0 M H Z
P L L 0 _ V D D A
D G N D
1 4 1
P L L 0 _ V S S A
R 9 2 3 5
Z _ S P D I F
1 4 2
n o _ u s e
O S C I N
1 4 3
H P S D 0 _ D S D 0 B
C 9 2 1 5
O S C V S S
1 4 4
1 8 P ( C H )
H W C K _ D S D 2 B
J 9 2 0 5
O S C O U T
0
1 4 5
R 9 3 0 0
H B C K _ D C L K
D S P 1 _ N _ R S T
R E S E T
1 4 6
1 0 0
C 9 2 1 8
H M C K
C V D D
1 4 7
M P I O _ B 1
R 9 2 5 2
0 . 1 / 1 0 ( B J )
R T C _ X I
N C P U _ S D O
1 4 8
1 0 0 K
C 9 2 1 9
M P I O _ B 0
R T C _ C V D D
N C P U _ W C K
1 4 9
M P I O _ C 3
N _ T R S T
0 . 1 / 1 0 ( B J )
T R S T
N C P U _ B C K
1 5 0
C 9 2 2 0
M P I O _ C 2
D V D D
N C P U _ M C K
1 5 1
M P I O _ C 1
T M S
0 . 1 / 1 0 ( B J )
T M S
N C P U _ S P D I F
1 5 2
M P I O _ C 0
R 9 2 8 9
T D I
T D I
1 5 3
C 9 2 2 1
M P I O _ A 3
C V D D
1 0 0 K
1 5 4
M P I O _ A 2
B T _ S P D I F
T C K
0 . 1 / 1 0 ( B J )
T C K
1 5 5
M P I O _ A 1
A V 1 _ D
T D O
T D O
1 5 6
M P I O _ A 0
A V 2 _ D
+ 3 . 3 D S P 1
G P 7 [ 1 4 ]
1 5 7
R 9 2 8 6
0 . 1 / 1 0 ( B J )
C 9 2 2 2
N P C M / I N T 1
D I R 1 _ N _ I N T
D V D D
1 5 8
E R R O R / I N T 0
3 3
R 9 2 8 7
C V D D
1 5 9
3 3
V +
0 . 1 / 1 0 ( B J )
C 9 2 2 3
+ 5 A
5
A H C L K X 1
1 6 0
C 9 2 2 4
3
C V D D
L 9 2 0 7
V -
1 6 1
B K P 1 0 0 5 H S 6 8 0 - T
0 . 1 / 1 0 ( B J )
A C L K X 1
J 9 2 1 0
1 6 2
+ 3 . 3 D R 1
0
A F S X 1
1 6 3
C 9 2 2 5
D V D D
C 9 2 5 4
D G N D
I C 9 3 8
1 6 4
4 7 0 0 P / 2 5 ( B )
1
R 9 2 4 2
D I R _ B C K
4
0 . 1 / 1 0 ( B J )
A C L K R 1
1 6 5
n o _ u s e
D I R _ W C K
2
A F S R 1
+ 3 . 3 D R 1
n o _ u s e
C 9 2 2 6
1 6 6
A G N D
D G N D
C V D D
D G N D
1 6 7
C 9 2 1 0
0 . 1 / 1 0 ( B J )
A X R 1 [ 8 ]
4 7 0 0 P / 2 5 ( B )
1 6 8
A X R 1 [ 7 ]
1 6 9
A X R 1 [ 6 ]
1 7 0
H W C K _ D S D 2 B
A X R 1 [ 5 ]
1 7 1
C 9 2 2 7
D V D D
C 9 3 1 5
1 7 2
H P S D 3 _ D S D 2 A
0 . 1 / 1 0 ( B J )
A X R 1 [ 4 ]
1 7 3
0 . 0 1 / 1 6 ( B )
H P S D 2 _ D S D 1 B
A X R 1 [ 3 ]
C 9 3 1 6
1 7 4
H P S D 1 _ D S D 1 A
A X R 1 [ 2 ]
1 7 5
0 . 0 1 / 1 6 ( B )
D I R _ S D O
A X R 1 [ 1 ]
C 9 3 1 7
1 7 6
0 . 0 1 / 1 6 ( B )
A G N D
D G N D
H D I G _ D S D 0 A
C 9 3 0 1
n o _ u s e
1 s t M P
C B 9 2 4
n o _ u s e
SERIAL
FLASH
+ 3 . 3 D S P
t o 0 0 4 . s h t ( H D M I T x )
to DIGITAL 4/8
IC926, 927: TC7SH32FU
VDD
1
54
VSS
2-input OR gate
DQ0
2
53
DQ15
VDDQ
3
52
VSSQ
4
51
DQ1
DQ14
Bank D
5
50
IN B
1
5
DQ2
DQ13
V
CC
Bank C
6
49
VSSQ
VDDQ
Bank B
DQ3
7
48
DQ12
DQ4
8
47
DQ11
IN A
2
VDDQ
9
46
VSSQ
10
45
DQ5
DQ10
11
44
DQ6
DQ9
GND
OUT Y
3
4
12
43
VSSQ
VDDQ
DQ7
13
42
DQ8
VDD
14
41
VSS
LDQM
15
40
NC
L(U)DQM
WE
16
39
UDQM
17
38
CAS
CLK
18
37
RAS
CKE
CS
19
36
NC
A13
20
35
A11
A12
21
34
A9
DQ
A10/AP
22
33
A8
32
A0
23
A7
24
31
A1
A6
25
30
A2
A5
A3
26
29
A4
VDD
27
28
VSS
G
H
+ 3 . 3 D R 1
+ 5 D S P
+ 3 . 3 D S P
+ 5 . 5 V
+
3
.
3
D
R
1
+ 5 . 5 V
+
5
D
S
P
+ 3 . 3 D S P
+ 3 . 3 D
+ 3 . 3 D
( 2 1 2 5 )
I C 9 3 2
3.3
5.0
3.3
J 9 2 1 1
n o _ u s e
n o _ u s e
Q 9 2 0 1
I C 9 3 0
I C 9 3 1
R A L 0 3 5 P 0 1
5
4
R P 1 3 0 Q 3 3 1 D - T R - F
R P 1 3 0 Q 5 0 1 D - T R - F
3
2
6
5
4
1
2
3
4
3
4
3
Q 9 2 0 2
Y C 2 8 8 A 0
Y C 2 8 9 A 0
1
2
1
2
1
2
3
1
D T A 0 4 4 E U B T L
R 9 2 5 1
1 0 0 K
C 9 2 6 6
D G N D
0 . 0 1 / 1 6 ( B )
D G N D
D G N D
D G N D
V c e h = 1 ~ 6 . 5 V
V c e h = 1 ~ 6 . 5 V
V c e l = 0 - 0 . 4 V
V c e l = 0 - 0 . 4 V
D G N D
C 9 2 0 8
C 9 2 9 7
n o _ u s e
n o _ u s e
E M B _ S D C K E
8 8
C 9 2 5 8
D V D D
SL/SR
8 7
C/SW
E M B _ C L K
0 . 1 / 1 0 ( B J )
8 6
E M B _ W E _ D Q M [ 1 ]
SBL/SBR
8 5
FL/FR
E M B _ D [ 8 ]
8 4
E M B _ D [ 9 ] /
8 3
E M B _ D [ 1 0 ]
8 2
D V D D
C 9 2 5 9
8 1
E M B _ D [ 1 1 ]
0 . 1 / 1 0 ( B J )
8 0
E M B _ D [ 1 2 ]
7 9
E M B _ D [ 1 3 ]
7 8
C V D D
C 9 2 6 0
DSP
7 7
E M B _ D [ 1 4 ]
0 . 1 / 1 0 ( B J )
7 6
C 9 2 6 1
D V D D
7 5
E M B _ D [ 1 5 ]
0 . 1 / 1 0 ( B J )
7 4
E M B _ D [ 0 ]
7 3
E M B _ D [ 1 ]
7 2
C 9 2 6 5
D V D D
7 1
E M B _ D [ 2 ]
0 . 1 / 1 0 ( B J )
7 0
C 9 2 6 7
C V D D
6 9
I C 9 2 1
E M B _ D [ 3 ]
0 . 1 / 1 0 ( B J )
6 8
C 9 2 6 8
C V D D
D 8 0 Y K 1 1 3 C P T P 4 0 0
6 7
E M B _ D [ 4 ]
0 . 1 / 1 0 ( B J )
Y D 9 9 8 A 0
6 6
C 9 2 7 9
D V D D
6 5
E M B _ D [ 5 ]
0 . 1 / 1 0 ( B J )
6 4
E M B _ D [ 6 ]
6 3
E M B _ D [ 7 ]
6 2
C 9 2 8 1
C V D D
6 1
E M B _ W E _ D Q M [ 0 ]
0 . 1 / 1 0 ( B J )
6 0
E M B _ W E
5 9
D G N D
C 9 2 8 2
D V D D
5 8
E M B _ C A S
0 . 1 / 1 0 ( B J )
5 7
C 9 2 9 0
C V D D
5 6
No replacement part available.
E M A _ W E
0 . 1 / 1 0 ( B J )
5 5
E M A _ D [ 7 ]
5 4
C 9 2 9 1
D V D D
5 3
E M A _ D [ 6 ]
0 . 1 / 1 0 ( B J )
5 2
E M A _ D [ 5 ]
5 1
C 9 2 9 2
C V D D
5 0
E M A _ D [ 4 ]
0 . 1 / 1 0 ( B J )
4 9
E M A _ D [ 3 ]
4 8
C 9 2 9 3
D V D D
4 7
E M A _ D [ 2 ]
0 . 1 / 1 0 ( B J )
4 6
E M A _ D [ 1 ]
4 5
C 9 3 0 0
C 9 2 9 8
n o _ u s e
n o _ u s e
R 9 2 4 5
R 9 2 4 7
n o _ u s e
n o _ u s e
R 9 2 2 5
4 . 7 K
R 9 2 2 6
S e r i a l F l a s h M e m o r y
4 . 7 K
8 M b i t
R 9 2 2 7
4 . 7 K
I C 9 2 3
B l a n k
R 9 2 2 8
R 9 2 4 4
4 . 7 K
P a r t N o .
V e n d e r
P a r t T y p e
n o _ u s e
R 9 2 1 7
S E R I A L F L A S H B O O T
Y D 7 6 2 A 0
W I N B O N D
W 2 5 Q 8 0 B V S S I G
1 0 K
Y E 0 5 8 A 0
M X I C
M X 2 5 L 8 0 3 5 E M 2 I - 1 0 G
8
7
6
5
Y E 0 0 5 A 0
E O N
E N 2 5 Q 8 0 A - 1 0 0 H I P
Y F 2 7 1 A 0
1
2
3
4
Y E 2 0 0 B 0
E M S T
F 2 5 L 0 8 Q A - 1 0 0 P A G 2 S
R 9 2 1 9
1 0 K
D G N D
IC929: R1172H121D-T1-F
IC930: RP130Q331D-TR-F
CMOS-based positive-voltage regulator IC
Voltage regulator
V
V
DD
4
5
OUT
V
DD
4
A
B
Y
H
H
H
L
H
H
Vref
H
L
H
L
L
L
Current Limit
CE
GND
Vref
1
2
CE
1
Pin No.
Symbol
Description
1
CE
Chip Enable Pin
2
GND
Ground Pin
Pin No.
Symbol
3
NC
No Connection
1
CE
4
V
DD
Input Pin
2
GND
5
V
Output Pin of Voltage Regulator
OUT
3
V
OUT
4
V
DD
I
J
K
to DIGITAL 5/8
to DIGITAL 6/8
t o 0 0 6 . s h t
t o 0 0 5 . s h t
( N e t / U S B )
( u - C o m )
D A C _ F L T
D A C _ F L T
S B L / S B R
D A _ S D _ S B
D A _ S D _ S B
S R L / S R R
D A _ S D _ S R
D A _ S D _ S R
C / S W
D A _ S D _ C S W
D A _ S D _ C S W
F L / F R
D A _ S D _ F
D A _ S D _ F
D A _ M C K
D A _ M C K
D A _ W C K
D A _ W C K
D A _ B C K
D A _ B C K
Z A D C _ M C K 1
Z A D C _ M C K 1
Z A D C _ B C K
Z A D C _ B C K
Z A D C _ W C K
Z A D C _ W C K
Z A D C _ S D O
Z A D C _ S D O
R 9 2 0 0 4 7
E M C K E
R 9 2 2 9 3 3
E M C L K
R 9 2 3 1 4 7
E M D Q M 1
E M D 8
SDRAM
E M D 9
+ 3 . 3 D S P 1
E M D 1 0
C 9 2 0 5
E M D 1 1
1 0 / 6 . 3
E M D 1 2
E M D 1 3
C 9 2 4 7
0 . 1 / 1 0 ( B J )
E M D 1 4
V C C
V S S
R 9 3 0 2
D Q 0
D Q 1 5
R 9 3 0 4
E M D 1 5
4 7 X 4
4 7 X 4
E M D 0
C 9 2 4 3
V C C Q
V S S Q
C 9 2 4 8
E M D 1 5
E M D 0
E M D 1
D Q 1
D Q 1 4
E M D 1 4
E M D 1
0 . 1 / 1 0 ( B J )
0 . 1 / 1 0 ( B J )
E M D 2
D Q 2
D Q 1 3
E M D 1 3
E M D 3
V S S Q
V C C Q
E M D 1 2
E M D 2
D Q 3
D Q 1 2
D Q 4
D Q 1 1
R 9 3 0 3
R 9 3 0 5
E M D 3
4 7 X 4
4 7 X 4
E M D 4
C 9 2 4 4
V C C Q
V S S Q
C 9 2 4 9
E M D 1 1
E M D 5
D Q 5
D Q 1 0
E M D 1 0
E M D 4
0 . 1 / 1 0 ( B J )
0 . 1 / 1 0 ( B J )
E M D 6
D Q 6
D Q 9
E M D 9
E M D 7
V S S Q
V C C Q
E M D 8
E M D 5
D Q 7
D Q 8
E M D 6
C 9 2 4 5
V C C
V S S
E M D 7
E M D Q M 0
D Q M L
N C
R 9 2 3 2
0 . 1 / 1 0 ( B J )
/ E M W E
W E
D Q M U
E M D Q M 1
4 7 X 4
E M D Q M 0
/ E M C A S
C A S
C L K
E M C L K
/ E M W E
/ E M R A S
R A S
C K E
E M C K E
/ E M C A S
/ E M C S 0
C S
N C
E M B A 0
A 1 3 / B A 0
A 1 1
E M A 1 1
E M B A 1
A 1 2 / B A 1
A 9
E M A 9
E M A 1 0
A 1 0 / A P
A 8
E M A 8
E M A 0
A 0
A 7
E M A 7
E M A 1
A 1
A 6
E M A 6
E M A 2
A 2
A 5
E M A 5
E M A 3
A 3
A 4
E M A 4
V C C
V S S
C 9 2 4 6
0 . 1 / 1 0 ( B J )
D G N D
S D R A M
6 4 M b i t
I C 9 2 2
+ 3 . 3 D S P
P a r t N o .
V e n d e r
P a r t T y p e
+ 1 . 2 D S P 1
+ 3 . 3 D S P 1
X 9 6 2 5 C 0
E S M T
M 1 2 L 6 4 1 6 4 A - 5 T G 2 M
X Z 4 1 4 F 0
W I N B O N D W 9 8 6 4 G 6 J H - 6
Y D 4 8 7 A 0
Z E N T E L A 3 V 6 4 S 4 0 E T P - G 6
D G N D
DIGITAL (1)
S h e e t 7 : D S P / D I R
I C / C B / X L : 9 2 1 - 9 3 9
O H T E R
: 9 2 0 1 - 9 3 9 9
IC931: RP130Q501D-TR-F
Voltage regulator
3
V
OUT
V
DD
4
3
V
OUT
Vref
Current Limit
Current Limit
2
GND
CE
1
2
GND
Description
Pin No.
Symbol
Description
Chip Enable ("H" Active)
1
CE
Chip Enable ("H" Active)
Ground Pin
2
GND
Ground Pin
Output Pin
3
V
OUT
Output Pin
Input Pin
4
V
DD
Input Pin
L
M
N
RX-V675/HTR-6066/RX-A730/TSR-6750
IC921: D80YK113CPTP400
Digital signal processor
JTAG Interface
DSP Subsystem
System Control
TM
C674x
DSP MICRO-
PLL/Clock
PROCESSOR
Input
Generator
Clock(s)
w/OSC
Memory Protection
I/O Protection
AET
General-
Purpose
32 KB
32 KB
Timer
L1 Pgm
L1 RAM
Power/Sleep
Controller
General-
256 KB L2 RAM
Purpose
RTC/
Timer
Pin
32-KHz
(Watchdog)
Multiplexing
1024 KB L2 ROM
OSC
Switched Control Resource (SCR)
Peripherals
DMA
Audio Ports
Serial Interface
GPIO
EDMA3
dMAX
McASP
I
2
C
SPI
UART
w/FIFO
Control Timers
Shared Memory
128 KB
eHRPWM
eCAP
eQEP
RAM
Connectivity
External Memory Interface
USB2.0
EMIFA(8b/16b)
EMIFB
MMC/SD
OTG Ctlr
HPI
NAND/Flash
SDRAM Only
(8b)
PHY
16b SDRAM
(16b/32b)
IC923: W25Q80BVSSIG
8 M-bit flash memory with dual and quad SPI
Security Register 3 - 0
to DIGITAL 8/8
003000h
0030FFh
002000h
0020FFh
001000h
0010FFh
000000h
0000FFh
Block Segmentation
0FFF00h
0FFFFFh
∙
∙
xxFF00h
xxFFFFh
∙
∙
Block 15 (64KB)
Sector 15 (4KB)
0F0000h
0F00FFh
xxF000h
xxF0FFh
xxEF00h
xxEFFFh
∙
∙
Sector 14 (4KB)
xxE000h
xxE0FFh
xxDF00h
xxDFFFh
∙
∙
Sector 13 (4KB)
xxD000h
xxD0FFh
∙
∙
∙
∙
∙
∙
xx2F00h
xx2FFFh
∙
∙
Sector 2 (4KB)
xx2000h
xx20FFh
08FF00h
08FFFFh
xx1F00h
xx1FFFh
∙
∙
Block 8 (64KB)
∙
Sector 1 (4KB)
∙
080000h
0800FFh
xx1000h
xx10FFh
xx0F00h
xx0FFFh
07FF00h
07FFFFh
∙
∙
∙
∙
Sector 0 (4KB)
Block 7 (64KB)
xx0000h
xx00FFh
070000h
0700FFh
Write Control
3
/WP(IO
2
)
Logic
∙
∙
∙
Status
Register
High Voltage
Generators
00FF00h
00FFFFh
∙
∙
Block 0 (64KB)
/HOLD(IO
3
)
7
000000h
0000FFh
Page Address
CLK
6
Latch / Counter
Beginning
Ending
SPI
Page Address
Page Address
/CS
1
Command
and
Column Decode
Control Logic
And 256-Byte page Buffer
Data
5
DI(IO
0
)
2
DO(IO
1
)
Byte Address
Latch / Counter
IC924: PCM9211PTR
216-kHz digital audio interface transceiver (DIX) with stereo ADC and routing
FILT
43
AUXIN0
AUTO
RXIN7
DIR
RXIN0
DIR
RXIN0
37
20
SCKO
DOUT
RXIN1
ADC
MAIN
RXIN1
35
PLL
19
BCK
OUTPUT
RXIN2
AUXIN0
RXIN2
33
SCKO/BCK/LRCK
PORT
18
LRCK
RXIN3
RXIN3
32
AUXIN1
17
DOUT
RXIN4
Lock:DIR
AUXIN2
RXIN4/ASCKIO
31
Unlock:ADC
RXIN5
Clock/Data
RXIN5/ABCKIO
30
Recovery
RXIN6
RXIN6/ALRCKIO
29
RXIN7
28
AUTO
RXIN7/ADIN0
DIR
RXIN8
Lock
ADC
MPIO_A0
3
Detection
DIT
RXIN9
AUXIN0
MPIO_A1
4
MPIO_A
SELECTOR
RXIN10
AUXIN1
MPIO_A2
5
MPIO_A3
RXIN11
RECOUT0
AUXIN2
6
DITOUT
RECOUT1
RECOUT0
MPO0/1
15
MPO0
RECOUT1
SELECTOR
ADC
DITOUT
16
MPO1
VINL
47
ADC Mode
ADC
VINR
48
Control
VCOM
44
Com. Supply
AUTO
DIR
MPIO_C0
7
ADC Standalone
11
MPIO_B0
ADC
MPIO_C1
8
MPIO_B
12
MPIO_B1
MPIO_C
AUXOUT
SELECTOR
AUXIN0
SELECTOR
MPIO_C2
9
13
MPIO_B2
AUXIN1
AUXIN2
MPIO_C3
AUXIN1
10
14
MPIO_B3
AUXIN2
ADC Clock
(SCK/BCK/LRCK)
Divider
XTI
39
OSC
XTO
40
SBCK/SLRCK
XMCKO
Secondary SCK/LRCK
XMCKO
(To MPIO_A and MPO0/1)
(To MPIO_A)
Divider
Divider
Selector
REGISTER
EXTRA DIR FUNCTIONS
MC/SCL
25
2
1
ERROR/INT0
SPI/I
C
Function
DIR CS
DIR
DIR
ERROR DETECTION
MDI/SDA
24
INTERFACE
2
NPCM/INT1
(48-bit)
PC
and
PD
IS
Calculator
Control
Non PCM DETECTION
MDO/ADR0
23
Is Calculator
MPIO_A
MS/ADR1
26
GPIO/GPO
DIT CS
DIR
All Port
Flags
DTS-CD/LD Detection
MPIO_B
Data
(48-bit)
Interrupt
IS
Calculator
Validity Flag
MPIO_C
User Data
MPO0
POWER SUPPLY
Channel Status Data
RST
34
Reset and
BFRAME Detection
MPO1
ADC
DIR
DIR
Mode
ALL
Interrupt System
MODE
27
ANALOG
ANALOG
ANALOG
Set
46
45
42
41
36
38
22
21
VCCAD AGNDAD VCC
AGND
VDDRX
GNDRX
DVDD
DGND
★ All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★ Components having special characteristics are marked
and must be replaced
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
133
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