LG -P990 Service Manual page 174

BASE BAND PROCESSOR
V_POWERRAIL V_BAT_CP
FB203 120
MEM_CKE
1.8V_SD MEM_BFCLKO1
MEM_SDLKO
MEM_STROBE1
MEM_STROBE0
MEM_DQM1
MEM_DQM0
MEM_CAS_N
MEM_RAS_N
MEM_CLE_N
MEM_WR_N
MEM_RD_N
MEM_ALE_N
MEM_CS1_N
MEM_CS0_N
MEM_BUSY
MEM_WP
3.1V_USB
1.2V_MIPI
2.5V_ANA2
1.8V_SD
C223 C224 C225 C226 C227
0.1u 0.1u 0.1u 0.1u 0.1u
1.8V_SD
C228
1.3V_CORE
0.1u
2.3V_RTC
C230
220n
X201
1 2
C231
FC-135
220n
C232 32.768KHz
18p
SYS_CLK
LGE Internal Use Only
R204
100
SWIF_TXRX
J6
MMCI3_DAT[3]
D1
MMCI3_DAT[2]
D2
MMCI3_DAT[1]
C1
MMCI3_DAT[0]
C2
MMCI3_CD
D4
MMCI3_CLK
PMIC
B1
MMCI3_CMD
B2
MMCI2_DAT[3]
E5
MMCI2_DAT[2]
D5
MMCI2_DAT[1]
D6
MMCI2_DAT[0]
D7
MMCI2_CD
G4
MMCI2_CLK
E4
MMCI2_CMD
D8
MEM_CKE
U11
MEM_BFCLKO_1
W14
MEM_BFCLKO_0
U14
MEM_SDCLKO
W13
MEM_BC3_n
Y17
MEM_BC2_n
U20
MEM_BC1_n
W15
MEM_BC0_n
U19
MEM_CAS_n
T14
MEM_RAS_n
T13
MEM_WAIT_n
U15
MEM_WR_n
U13
MEM_RD_n
U12
MEM_ADV_n
V15
MEM_CSA0_n
T11
MEM_CS2_n
T12
MEM_CS1_n
R12
MEM_CS0_n
P12
FCDP_RBn
T9
FWP
V9
VDD_FUSE_FS
P8
VDD_FUSE_LS
P9
VDD_USB_HS_PHY
D9
VDD_USB_DIG
D10
VDD_USB
C9
VDD_MIPI_SLAVE
W7
VDD_MIPI_MASTER
W11
VDD_MIPI_BGC
W8
VDD_MIPI_PLL
W12
R226 30K MIPI_R_EXT
W10
VDDP_MMC
N10
VSS_MAIN_19
W9
VSS_MAIN_18
V12
U202
VSS_MAIN_17
M3
VSS_MAIN_16
J3
VSS_MAIN_15
H20
VSS_MAIN_14
P7
VSS_MAIN_13
G7
VSS_MAIN_12
R4
VSS_MAIN_11
F4
VSS_MAIN_10
D16
VSS_MAIN_9
D11
VSS_MAIN_6
T16
VSS_MAIN_5
T7
VSS_MAIN_4
L11
VSS_MAIN_3
K7
VSS_MAIN_2
E7
VSS_MAIN_1
B11
VDDP_DIG_MS
H14
VDDP_DIG_6
R3
VDDP_DIG_5
F3
VDDP_DIG_4
U17
VDDP_DIG_3
T6
VDDP_DIG_2
K8
VDDP_DIG_1
E6
VDD_CORE_6
R5
VDD_CORE_5
F5
VDD_CORE_4
T15
VDD_CORE_3
T8
VDD_CORE_2
K11
VDD_CORE_1
E9
VSS_RTC
C12
VDD_RTC
B12
OSC32K
A11
F32K
A12
F26M
D13
C233
18p
Close to X101
need to apply 43.2ohm, 1%
PT201
10K
C201 10n
C202 220n
1.3V_ANA1(Internal connect)
C216 220n
C205 220n
C206 1u
C213 1u
C214 0.1u
C209 220n
C210 0.1u
C211 220n
C207 1u
C208 0.1u
C212 0.1u
TP203 IPC_MRDY
IFX1_AP20
TP208
TP202 IPC_SRDY
TP209
IFX2_AP20
CSI_CLKN
Y7
CSI_CLKP
Y8
CSI_DN2
Y5
CSI_DP2 IFX_USB_VBUS
Y6
CSI_DN1
Y9
CSI_DP1
Y10
CIF_RESET_GPIO
R2
CIF_PD_GPIO
T1
CLKOUT2
T2
CIF_VSYNC
T4
CIF_HSYNC
T5
CIF_PCLK
U1
CIF_D7
U2
CIF_D6
V1
CIF_D5
V2
CIF_D4
W1
CIF_D3
W2
CIF_D2
W3
CIF_D1
Y2
CIF_D0
Y3
I2S1_WA0
DAP3_PCM_FS
H7
I2S1_TX DAP3_PCM_DOUT
H5
I2S1_RX DAP3_PCM_DIN
H8
I2S1_WA1
J7
I2S1_CLK0 DAP3_PCM_SCLK
J8
I2C2_SDA
J1
I2C2_SCL
J2
I2C1_SDA
H1
I2C1_SCL
H2
CP2
M19
CP1
M20
VDD_CPN
M18
VUMIC
M16
VMIC
L16
HP_SPK2N
L19 V_BAT_CP
HP_SPK2P
L20
HP_SPK1N
K19
HP_SPK1P
J20
VSS_HF_SPK_2
J18
VSS_HF_SPK_1
H19
VBAT_HF_SPK_2
J19
VBAT_HF_SPK_1
K20
MIPI1_DATA7
U8
MIPI1_DATA6
U7
MIPI1_DATA5
U6
MIPI1_DATA4
U5
MIPI1_DATA3
U4
MIPI1_DATA2
W6
MIPI1_DATA1
W5
MIPI1_DATA0
W4
MIPI1_CLK
Y4
MEM_AD15 MEM_AD15
U16
MEM_AD14 MEM_AD14
P13
MEM_AD13 MEM_AD13
P14
MEM_AD12 MEM_AD12
N13
MEM_AD11
MEM_AD11
T17
MEM_AD10 MEM_AD10
R16
MEM_AD9 MEM_AD9
N14
MEM_AD8 MEM_AD8
R17
MEM_AD7 MEM_AD7
P16
MEM_AD6 MEM_AD6
R18
MEM_AD5 MEM_AD5
P17
MEM_AD4 MEM_AD4
N16
MEM_AD3
MEM_AD3
N17
MEM_AD2 MEM_AD2
P19
MEM_AD1 MEM_AD1
N19
MEM_AD0 MEM_AD0
N20
MEM_A15 MEM_A15
Y16
MEM_A14 MEM_A14
Y15
MEM_A13 MEM_A13
W16
MEM_A12 MEM_A12
W17
MEM_A11 MEM_A11
W18
MEM_A10
MEM_A10
Y18
MEM_A9 MEM_A9
W19
MEM_A8 MEM_A8
Y19
MEM_A7 MEM_A7
W20
MEM_A6 MEM_A6
V19
MEM_A5 MEM_A5
V20
MEM_A4 MEM_A4
T19
MEM_A3 MEM_A3
T20
MEM_A2
MEM_A2
R19
MEM_A1 MEM_A1
R20
MEM_A0 MEM_A0
P20
(Active high connected to default pull down GPIO of AP20H)
- 174 -
ON BOARD JTAG(CP)
2.3V_RTC
1.8V_SD
CN201
1 10
TCK
2 9
TRSTN TRIG_IN 2.3V_RTC
3 8
TDI TDO
U201
4 7
1 5
TMS _OE VCC
2
5 6 A
3 4
GND Y
BOOT CONFIGURATION
1.8V_SD
1.8V_SD
DSP_AUDIO_IN1
HW_MON1
HW_MON2
IFX_I2C_SDA TRIG_IN
IFX_I2C_SCL
DSP_AUDIO_IN1 HW_MON1 HW_MON2 TRIG_IN
16-bit NAND boot 0 1 1 0
Flashless boot
1 1 1 0
C222
NOR boot 0 0 1 0
220n
Analog switch for USIF1
U203
V_BAT_CP 1 7
VCC 2B0 UART1_IPC_RXD
2 6
UART_RX_SW 1B1 GND
C229
0.1u
VBUS_OUT
IFX_USB_VBUS
Q201
1 S1 D1 6
IFX_USB_VBUS_EN 2 G1 G2 5
3 D2 S2 4
Copyright © 2011 LG Electronics. Inc. All right reserved.
7. CIRCUIT DIAGRAM
RESET1_N
USIF1_SW
Only for training and service purposes