Engine Pcb-Mara Clock, Delay Memory, Scanport, Cpld (3 Of 5) - Kurzweil sp5-8 Service Manual

Engine PCB—MARA Clock, Delay Memory, ScanPort, CPLD (3 of 5)
5
VCC33
L8
VCC33_ISO_U14
VCC33 600 OHM @ 100MHz C103
0.1uF
DNS
R35
D
J8 Y2
10K
1 1 4
EN VCC33
2
2 3
GND OUT
HEADER2 12.2880 MHz
OSC DISABLE
J9 DNS
1
2
HEADER2
FUNC GEN
VCC33
C105
0.1uF
U7A
2 6
C
NC7WZ125
sh.1,5 CPU_WR_L
U7B
5 3
NC7WZ125
sh.2 DDR_D_[15:0]
sh.2 DDR_A_[12:0]
B
C118
0.1uF
sh.2 DDR_VREF
C119
R47
10K
0.1uF
sh.2 DDR_BA_[1:0]
sh.2 DDR_CAS_L
sh.2 DDR_RAS_L
sh.2 DDR_WE_L
sh.2 DDR_CLK_L
sh.2 DDR_CLK_H
sh.2 DDR_CKE
A
5
4
R36
DAC_CLK12_288 sh.4
33
M1_CLK12_288_IN sh.2
R39 22
MARA_WR_L sh.2
R45 22
CPU_WR_BUF_L sh.4
VCC25
C113 C112 C114 C115 C116 C117
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
DDR RAM VCC25 VCC25
VCC25
U12
R46
10K
49 65 DDR_D_15
VREF DQ15
63 DDR_D_14
DQ14
17 62 DDR_D_13
A13 DQ13
DDR_A_12 42 * 60 DDR_D_12
A12 DQ12
DDR_A_11 41 * 59 DDR_D_11
A11 DQ11
28 57
DDR_A_10 DDR_D_10
A10 DQ10
DDR_A_9 40 56 DDR_D_9
A9 DQ9
DDR_A_8 39 54 DDR_D_8
A8 DQ8
DDR_A_7 38 13 DDR_D_7
A7 DQ7
DDR_A_6 37 11 DDR_D_6
A6 DQ6
DDR_A_5 36 10 DDR_D_5
A5 DQ5
DDR_A_4 35 8 DDR_D_4
A4 DQ4
32 7
DDR_A_3 DDR_D_3
A3 DQ3
DDR_A_2 31 5 DDR_D_2
A2 DQ2
DDR_A_1 30 4 DDR_D_1
A1 DQ1
DDR_A_0 29 2 DDR_D_0
A0 DQ0
27 51
DDR_BA_1
DDR_DQS_2
BA1 UDQS
DDR_BA_0 26 16
BA0 LDQS DDR_DQS_0
22 47
CAS UDM
23 20
RAS LDM
21
WE
24
CS
MT46V8M16P-75
46
CK
45
CK
44
CKE
4
3
sh.1,2,4,5 CPU_D_[7:0]
CPU_D_7
CPU_D_6
CPU_D_5
CPU_D_4
CPU_D_3
CPU_D_2
CPU_D_1
CPU_D_0
74HC245
sh.1,5 SCAN_CS_L
sh.4 CPU_WR_BUF_L
sh.1 SPANA_OUT1
sh.1,4 BRITE
(SPANA_OUT2)
SPRES_L
SPREN_KY_L
SPREN_SW_L
SPEN_AN_L
SPWEN_LED_L
R40 10K
74HC245
SPEN_L
VCC33
C106
U10 0.1uF
2 4 SPBLANK_L
sh.1 SPBLANK
NC7S04
ARPY
CPLD
SPREN_KY_L
SPREN_SW_L
SPWEN_LED_L
sh.1 BOOT_FL_CS_L
SPRES_L
sh.1 BOOT_E_CS_L
sh.1,5 ADTRG_L
sh.1 BOOT_FL_OE_L
sh.1,5 FLASH_CS_L
sh.1,4,5 CPU_RD_L
sh.4 LCDE
SPEN_AN_L
sh.1,5 RESET_L
sh.1,5 SDRAM_CLK
BiDir
sh.1,2,5 CPU_WAIT_L
sh.1,5 SCAN_CS_L
sh.2 sh.1,5 UART_CS_L
sh.2 sh.1,5 CPU_A_20
VCC33
C120
0.1uF
J10
1 2
3 4 CPLD_TMS
5 6 CPLD_TCK
7 8 CPLD_TDO
9 10 CPLD_TDI
11 12
13 14
HEADER 7X2
Xilinx Parallel Cable
3
2
SCAN PORT INTERFACE VCC33
VCC33
RN23 RN24
10K
10K
C102
0.1uF
U6
RN25 150
18 2 8 1
B0 A0
17 3 7 2
B1 A1
16 4 6 3
B2 A2
15 5 5 4
B3 A3
14 6 8 1
B4 A4
13 7 7 2
B5 A5
12 8 6 3
B6 A6
11 9 5 4
B7 A7
1 RN26 150
DIR
19
OE
SPANA_IN_P
SPANA_IN_N
VCC33
C104
0.1uF
U8
RN27 150
18 2 8 1 B_SPRES_L
B0 A0
17 3 7 2 B_SPREN_KY_L
B1 A1
16 4 6 3 B_SPREN_SW_L
B2 A2
15 5 5 4 B_SPEN_AN_L
B3 A3
14 6 8 1
B_SPREN_LED_L
B4 A4
13 7 7 2 B_SP_TBD1
B5 A5
12 8 6 3
B6 A6
11 9 5 4 B_SPBLANK_L
B7 A7
1
RN28 150
DIR
19
OE
RN29 RN30
10K
10K
VCC33
B_SP_TBD2
SPEN_L
VCC33
C108 C109 C110
0.1uF 0.1uF 0.1uF
U11
R101
38 28
I/O I/O FLWR_L sh.1
37 27 0
I/O I/O
32 23
MARA_1_CS_L
I/O I/O
31 22
I/O I/O MARA_CS_L
30 21
I/O I/O UART_RD_L sh.1
29 20
I/O I/O UART_WR_L sh.1
19
I/O DSP_RESET_SEL_L sh.1,5
3 18
CPU_A_21 sh.1,5
I/O I/O
2
I/O
42 16
I/O I/O FLRD_L sh.1
41 14
I/O I/O BOOT_CS_L sh.1,5
40 13
I/O I/O LCD_CS_L sh.1,4,5
39 12
CPU_A_19 sh.1,5
I/O I/O
8
DSP_RESET_L sh.2,5
I/O
7
CPU_WR_BUF_L sh.4
I/O
1 6
I/O/GCK3 I/O
44 5
I/O/GCK2 I/O EPROM_INST_L sh.1
43
I/O/GCK1
34
I/O/GTS2
36
I/O/GTS1
33
I/O/GSR
9 24
TDI TDO
11
TCK
10
TMS
XC9536XL
2
SP5-8 Service Manual
1
VCC33
L14
600 OHM @ 100MHz
J7
1
SPD_0 2
SPD_1 3
D
SPD_2 4
SPD_3 5
SPD_4 6
7
SPD_5
SPD_6 8
SPD_7 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
HEADER 13X2
SH_AVCC sh.1
R37
R38 D3
3.32K
BAS70H
U9A
10.0K
2 R41
-
1
SH_AN0 sh.1
R42 3
+ 1.00K
NJM4580E
D4
10.0K C
R43
BAS70H
SH_AVCC sh.1
6.65K
R44 Connect to SH-2A AVREF pin
6.65K
Place Circuit Close to SH-2A ADC pins
+12V
C107
U9B
6 0.1uF
-
7
5
+
NJM4580E
C111
0.1uF
-12V
B
sh.1, 5
sh.2
A
Young Chang R&D Institute
1432 Main St.
Waltham MA 02451
USA Copyright 2010 Young Chang Co., Ltd.
Reproduction without the express written consent of Young Chang Co., Ltd. is prohibited.
Title
PC3LE ENGINE BOARD
MARA CLOCK, DELAY MEMORY, SCAN PORT, CPLD
Size By Document Number Rev
R. Folk 021402
F V1
Date: Wednesday, April 04, 2012 Sheet 3 of 5
1
7-5